Polycrystalline silicon resistors for integrated circuits

The suitability of thin films of doped polycrystalline silicon on SiO₂ substrates for the production of high value resistors for monolithic integrated circuits is considered. Resistors fabricated from this material posses the advantages of high sheet resistivity and dielectric isolation while still preserving an all silicon technology compatible with conventional production techniques.Relevant structural and electrical properties of doped polycrystalline films produced by both vacuum evaporation onto hot substrates with gas-doping and by diffusion-annealing of amorphous films have been investigated. Sheet resistivities and TCR values measured on 2500 Å polycrystalline films have proved superior to those encountered with conventional diffused resistors. Typically films with sheet resistivities of 1 kΩ/□ had TCR's of ?1000 ppm/°C while conventional diffused resistors are generally made from material of 200 Ω/□ and +2000 ppm/°C TCR. Etched resistor line widths of 0·25 mil. have been obtained in the polycrystalline material employing conventional photolithographic techniques. The temperature stability and linearity of doped polycrystalline resistors have been investigated.     

Silicide resistors for integrated circuits

Thin-film resistors are useful in monolithic integrated circuits whenever high sheet resistance (ρs> 1 kΩ/sq) or radiation hardness are required. Silicide resistive films (MoSi2, CrSi2, and Si-Cr) deposited by dc sputtering have been shown to be compatible with monolithic circuit production end require no protective overlayer. Si-Cr films 200-300 Å thick have ρs, and temperature coefficients of resistance (TCR) ranging from about 1 kΩ/sq and +150 ppm/°C (CrSi2) to 20 kΩ/sq and -1400 ppm/°C (17 at % Cr). MoSi2is best suited for resistor applications requiring 100-200Ω/sq. MoSi2films are about 700 Å thick at 200 Ω/sq, compared to < 100 Å for 200-Ω/sq Ni-Cr, and their TCR is -125 ppm/°C. Typical stability for unprotected silicide resistors in TO-5 packages at 200°C, no load, is < ±3 percent during the first 200 h and < ± 0.5 percent during the next 2000 h. The films are stable during short term exposure to high temperatures as encountered during monolithic or hybrid circuit ceramic package sealing.     

Arsenic-doped polycrystalline silicon film for bipolar integrated circuits

The advantages of the use of As-doped polycrystalline silicon film over that of As-doped glass film in the fabrication of high speed bipolar integrated circuits have been shown. The films have been used for doping buried layer and emitter. Deposition conditions optimized for the As-doped polycrystalline silicon film allows low junction leakage to be attained with low pipe density. During the course of the work the mechanism for the formation of pipes have been suggested.     

FEN filter design using tantalum and silicon integrated circuits

An economical approach to integrated active RC filter design is described. Complex filter networks are broken down into a series of cascadable second-order filter sections consisting of tantalum thin-film RC networks and semiconductor integrated operational amplifiers. Two building blocks are available for any desired frequency within a decade and for any desired filter function (e.g., low-pass, high-pass, band-pass, band-reject, all-pass, etc.). One building block is for low Q realizations and contains one amplifier; the other is for high Q realizations and contains two. The considerable versatility of this approach is obtained by 1) a network synthesis approach based on decomposing a given second-order function into a low Q asymptotic approximation of this function in cascade with an active frequency emphasizing network and 2) by the characteristics of tantalum and silicon integrated circuits.     

Large-value monolithic resistors for micropower integrated circuits

The minimum power dissipation of micropower integrated circuits is often limited by the availability of large-value monolithic resistors. Two major types of field-effect resistor structures are examined and an analysis of the primary factors that determine sheet resistance and parasitic capacitance is presented. Resistor tolerance, linearity, and temperature coefficient are briefly discussed. It is shown that resistors with sheet resistances greater than 50 k/spl Omega///spl square/ and parasitic capacitances less than 0.002 pF/k/spl Omega/ can be readily fabricated in a monolithic structure.     

Precision thin-film cermet resistors for integrated circuits

The use of thin-film resistors in monolithic integrated circuits is becoming more widespread as the performance requirements imposed upon circuit designers become more stringent. A cermet, consisting of a mixture of Cr and SiO, was selected as a suitable resistor mterial for this purpose because of its compatibility with semiconductor materials and processes, and because of its stability and reproducibility over a wide range of sheet resistance. Cermet films with sheet resistances of 300, 1000, and 2000 Ω/square were flash evaporated on silicon substrates, and resistors were fabricated. The techniques for depositing the cermet films and fabricating the resistors are discussed, and methods for subsequently adjusting the resistors to precise values are described. The properties of the completed resistors are presented in detail.     

Termination materials for thin film resistors

The resistance of a thin film resistor can be considered as consisting of three parts: 1) the resistance of the resistor material, 2) the resistance of the termination material, and 3) the interfacial resistance. The aging of the interfacial resistance can dominate the aging of low valued resistors, especially under corrosive conditions. The interfacial resistance using a distributed parameter analysis is treated and a figure of merit which can be used to describe the aging of the interface is defined. Also, a sensitive method of measuring this quantity is introduced and a sampling of data on several different termination material systems is presented. The best results were obtained with Ti-Pd-Au. The conclusions drawn from the figure of merit are corroborated by adhesion and thermocompression bond strength studies.     

The stability of polycrystalline silicon thin film resistors measured using excess noise

The resistance of thin films of polycrystalline silicon prepared by chemical vapour deposition is found to vary with time and with cycling the temperature or strain. These variations of resistance are compared with the magnitude and variations of the excess, , noise which is known to be an equilibrium resistance fluctuation. The noise is found to be sensitive to the detailed state of the specimen.     

A new computer-aided simulation model for polycrystalline silicon film resistors

A general transport theory for the I–V characteristics of a polycrystalline film resistor has been derived by including the effects of carrier degeneracy, majority-carrier thermionic-diffusion across the space charge regions produced by carrier trapping in the grain boundaries, and quantum mechanical tunneling through the grain boundaries. Based on the derived transport theory, a new conduction model for the electrical resistivity of polycrystalline film resitors has been developed by incorporating the effects of carrier trapping and dopant segregation in the grain boundaries. Moreover, an empirical formula for the coefficient of the dopant-segregation effects has been proposed, which enables us to predict the dependence of the electrical resistivity of phosphorus-and arsenic-doped polycrystalline silicon films on thermal annealing temperature.Phosphorus-doped polycrystalline silicon resistors have been fabricated by using ion-implantation with doses ranged from 1.6 × 10¹¹ to 5 × 10¹⁵/cm². The dependence of the electrical resistivity on doping concentration and temperature have been measured and shown to be in good agreement with the results of computer simulations. In addition, computer simulations for boron-and arsenic-doped polycrystalline silicon resistors have also been performed and shown to be consistent with the experimental results published by previous authors.     

Thin film silicon on insulator substrates and their application to integrated circuits

Thin film silicon on insulator (TFSOI) devices have been studied for years. The advantages of TFSOI devices include: a reduction in junction capacitance, potentially lower junction leakage, a simpler process, and many other well documented advantages. However, other than some military/space applications, TFSOI circuits are not currently available in commodity products. One of the reasons TFSOI circuits are not wide spread is that there has not been a reliable source of TFSOI substrates. Recently, however, several suppliers of TFSOI substrates, both SIMOX and bonded and etch-backed wafers (BESOI), have made significant improvements in their material quality and are increasing capacity to meet expected demands. In this paper, we will discuss the major materials issues and how these issues impact either the TFSOI device performance or the process integration. In addition, we will present gate oxide integrity data as well as device results from these TFSOI substrates.     

Metallization systems for silicon integrated circuits

An investigation into single and composite layered metallization systems is described with respect to their limitations, possible failure mechanisms, and problems encountered in fabrication. Systems investigated include metals such as chromium, titanium, tungsten, and molybdenum in conjunction with gold. Comparisons are made to conventional aluminum with respect to ohmic contact to silicon, metallurgical reactions, behavior in adverse environmental conditions, method of deposition, and processing difficulties.     

A prediction technique for single-event effects on complex integrated circuits

The sensitivity of complex integrated circuits to single-event effects is investigated. Sensitivity depends not only on the cross section of physical modules but also on the behavior of data patterns running on the system. A method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of data patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules, a universal method to predict SEE sensitivities of different test patterns is proposed, which is verified by experiments based on the target circuit of a microprocessor. Experimental results show that the deviation between prediction and experiment is less than 20%.     

激光直写制备薄膜铂电阻技术研究

为了研究激光直写技术在制备薄膜铂电阻中的应用,采用激光直写制备了薄膜厚度为2m的铂电阻。探讨了激光直写技术制备薄膜铂电阻的原理,以条形铂电阻为例,研究了激光参量对铂电阻形状的影响,在最优的激光脉冲频率18kHz、激光扫描速率100mm/s的参量下,制备了实际电阻约为0.37的条形薄膜铂电阻,最后检验了薄膜铂电阻的电阻值。结果表明,铂电阻的宽度分别随激光脉冲频率和激光扫描速率的增大而增大;制备的电阻边缘整齐,表面平整,电阻实际值与理论值只有0.8%的相对误差,吻合很好。     

An investigation into the termination resistance of thin film resistors

A mathematical analysis of the termination resistance of thin-film resistors is given and a method of measuring this type of resistance is discussed. As examples, the termination resistances of sputtered and evaporated thin-film resistors have been measured. Relevant parameters of the termination to be specified are discussed.     

Reactively sputtered tantalum pentoxide thin films for integrated capacitors

The aim of this work was to develop a deposition process for a high-dielectric constant tantalum pentoxide for integrated capacitors. Thin films were deposited reactively on glass wafers using a radio-frequency magnetron sputtering cluster tool at various O₂/Ar flow ratios. By using 2 MeV ⁴He⁺ backscattering spectroscopy and X-ray diffraction, the films obtained showed a stoichiometric orthorhombic β-Ta₂O₅ phase at 20% O₂ in the sputtering gas flow. With low-frequency measurements (f=100 kHz), a 200×200-μm² square metal–insulator–metal (MIM) capacitor with copper electrodes and a 340-nm thick dielectric gave a capacitance density of 0.066 μF/cm², with a quality factor (Q) of 650. The value of the relative permittivity (_r) was approximately 25 determined from MIM capacitors of various sizes. The surface roughness of the 376-nm thick oxide film was found to be small: 0.255 nm. The largest measured capacitor (200×200 μm²) gave reasonable results at low frequencies. When the frequency was increased (100 kHz–20 GHz) only for the smaller capacitors (30×30 μm²) the capacitance remained constant. However, the Q values decreased of the smaller capacitors as a function of frequency. Processed tantalum pentoxide MIM capacitors possessed reasonable electrical properties below 2 GHz and good potential for further improvement.     

Compensation technique for DC and transient instability of thin film transistor circuits for large-area devices

A reliable driving scheme that can compensate for the inherent instability of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) is essential for implementation of large-area devices including displays and sensor arrays for bio-imaging applications. In particular, for high precision and high-resolution devices, the technique should be accurate and fast. A new driving scheme is presented that enables control of the DC and transient shift in the threshold voltage (V _T ) and gate voltage of drive/amplifier TFT, while fulfilling the timing requirements for the different applications. The transient shift in the gate voltage has been known to contribute as much as 10% error in controlling the DC shift in the V _T whereas it is less than 0.5% for the driving scheme presented here.     

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.     

Reverse photolithographic technique for thick film circuits

This paper deals with the reverse photolithographic technique, applied for the first time for the processing of thick film components on alumina substrates. The SEM photographs of the delineated patterns have revealed excellent edge line definition which is always saw-tooth shaped in the conventional process. Various VLSI application potentials have also been pointed out.     

A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.