DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.     

From synchronous to GALS: A new architecture for FPGAs

The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility. Consequently, this paper proposes a novel Field-Programmable Gate Arrays (FPGA) architecture that is compatible with existing devices and that can also support GALS designs. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but it must also include a minimal amount of basic components to prevent metastability for efficient asynchronous communications. Thus, the paper presents the constraint equations required to implement such a circuit. It also presents a pausible clock generator application and simulation results for the proposed architecture. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies.     

基于STG与Petrify的异步电路设计

随着集成电路设计工艺的进步,异步电路相对于同步电路的优越性将越来越明显,异步技术也将越来越成为研究的热点,预计未来集成电路设计将会更多地采用异步技术。Petri网具有的一些特性非常适用于异步电路设计。通过采用petri网的一类子系统STG设计异步电路,并使用一个异步电路设计工具Petrify完成整个设计过程。     

低功耗异步LDPC解码器运算通路设计

本文设计了异步LDPC解码器运算通路,利用异步电路减少信号到达时间不一致引起的毛刺和时钟引起的功耗.利用输入数据的统计特性设计了运算通路中的主要运算单元,减少了冗余运算.本文还实现了同步运算通路和基于门控时钟的运算通路作为比较.三种设计采用相近的架构,在0.18μm CMOS工艺下实现相同的功能.仿真结果表明,提出的异步设计功耗最小,相比于同步设计和基于门控时钟设计,分别节省了42.0%和32.6%的功耗.虽然性能稍逊于同步设计,但优于门控时钟设计.其中,同步设计的延时是1.09ns,基于门控时钟的设计延时是1.61ns,而异步设计则是1.20ns.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

JR系列电动机同步化的实验研究

以JR系列电机为例分析了绕线式异步电动机同步化的可能性和原理,并对转子绕组的改接方式作了讨论,实验表明,绕线式异步时机的步同化是可行的,替代同步发动机具有一定的实际意义。     

异步Viterbi解码器同步接口的设计

提出了一种利用异步 FIFO ( First In First Out)连接异步逻辑电路与同步逻辑电路的方法 ,并设计实现了相应的异步 FIFO电路 ,作为连接异步 viterbi解码器和其他同步逻辑电路的同步接口。对异步 FIFO的级数与异步 viterbi解码器内部的时序关系进行了分析。用逻辑仿真的动态时序分析表明 ,当同步电路时钟的周期大于 130 ns时 ,具有同步接口的异步 viterbi解码器可以与同步电路正常协同工作。具有简单接口电路的异步解码器 ,既能发挥异步电路功率效率高的优点 ,而且能嵌入同步电路系统     

Asynchronous Techniques for System-on-Chip Design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.     

切换成功率的改善

从现网统计发现同步切换与异步切换的切出数量比大约是1：4,异步切换的切出成功率比同步切换的切出成功率高1．6％,为了提高切出成功率,通过对同步切换的切出成功率低的原因进行细致分析,得出将同步切换调整为异步切换的合理性,并在现网推广实施后,有效改善了切出成功率。     

基于CDP1854的智能数据适配器设计与使用

异步接收/同步发送数据适配器是PC机与受控终端之间实现信息交换的接口电路。为了实现信息传送,需要将从PC机串口发送来的串行异步信息转换为同步信息发送出去,该适配器可实现异步接收/串行发送,达到PC机控制受控终端的目的。     

异步保密机中密码滚动探讨

用数论变换实现的异步保密机中，再采用密码滚动，提高密钥量和通信的可靠性。在密钥滚动、同步建立、帧失步修正等方面作了尝试性的工作。     

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design

The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.     

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology

This paper presents a scan chain design for dual-rail asynchronous circuits. This is a true asynchronous scan chain because no clock is needed even in scan mode. This is a full-scan design for testability (DfT) so only combinational automatic test pattern generation (ATPG) is needed and the fault coverage of generated test patterns is very high. This technique can be applied to various kinds of asynchronous circuits, including pipelines, state machines, and interconnects. Experiments on an 8051 datapath circuit show that the coverage is as high as 99.59%. This technique has been proven to work successfully in 8 μm Thin-film transistor (TFT) technology on the glass.     

Designing asynchronous standby circuits for a low-power pager

We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40% larger in size than synchronous designs. For the total pager unit this means a 37% reduction in power dissipation for nearly no additional area. The decoded chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In an appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size     

无线Mesh网中的Quorum节能机制

无线Mesh网络节能问题十分重要。文章讨论的基于Quorum的节能机制对网络规模、节点密度、移动性和多跳等因素不敏感,非常适合无线Mesh网络。Quorum节能机制主要基于MANET网络环境设计。Quorum系统根据时钟同步的难易程度,可以应用于同步和异步两种工作模式。目前对Quorum节能系统的研究主要集中在能量效率优化和自适应系统方面。对于异步和同步两种模式的协同,基于Quorum机制的节能与功率控制、MAC路由结合的跨层设计,是值得尝试的课题。     

Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays

Test and validation of embedded array blocks remains a major challenge in today's microprocessor design environment. The difficulty comes from twofold, the sizes of the arrays and the complexity of their timing and control. This paper describes a novel test generation methodology for test and validation of microprocessor embedded arrays. Unlike traditional ATPG methods, our test generation method is based upon the high-level assertion specification which is originally used for the purpose of formal verification. The superiority of these assertion tests over the traditional ATPG tests will be discussed and shown through various experiments on recent PowerPC microprocessor designs.     

Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory

Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared.     

一种适用于通信系统的异步加-选择-比较器

介绍了一种适用于Viterbi解码器的异步ACS(加法器-比较器-选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4-bit ACS,并通过0.6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75.5mW.由于采用异步控制,芯片在"睡眠"状态待机时不消耗动态功耗.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.通过与相同工艺下的同步4-bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.     

Fairness in MIMD Congestion Control Algorithms

The Mulitplicative Increase Multiplicative Decrease (MIMD) congestion control algorithm in the form of Scalable TCP has been proposed for high speed networks. We study fairness among sessions sharing a common bottleneck link, where one or more sessions use the MIMD algorithm. Losses, or congestion signals, occur when the capacity is reached but could also be initiated before that. Both synchronous as well as asynchronous losses are considered. In the asynchronous case, only one session suffers a loss at a loss instant. Two models are then considered to determine which source looses a packet: a rate dependent model in which the packet loss probability of a session is proportional to its rate at the congestion instant, and the independent loss rate model. We first study how two MIMD sessions share the capacity in the presence of general combinations of synchronous and asynchronous losses. We show that, in the presence of rate dependent losses, the capacity is fairly shared whereas rate independent losses provide high unfairness. We then study inter protocol fairness: how the capacity is shared in the presence of synchronous losses among sessions some of which use Additive Increase Multiplicative Decrease (AIMD) protocols whereas the others use MIMD protocols.     

Wave-pipelined intra-chip signaling for on-FPGA communications

On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.