Status and Trends in Advanced SOI Devices and Materials

A review of recently explored effects in advanced SOI devices and materials is given. The effects of key device parameters on the electrical and thermal floating body effects are shown for various device architectures.Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. New hot carrier phenomena are discussed. The effects of gate misalignment or underlap,as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

硅膜厚度对0.1μm SOI槽栅NMOS器件特性的影响

SOI技术和槽栅MOS新器件结构是在改善器件特性方面的两大突破,SOI槽栅MOS器件结构能够弥补体硅槽栅MOS器件在驱动能力和亚阈值特性方面的不足,同时也保证了在深亚微米领域的抑制短沟道效应和抗热载流子效应的能力.仿真结果显示硅膜厚度对SOI槽栅MOS器件的阈值电压、亚阈值特性和饱和驱动能力都有较大影响,选择最佳的硅膜厚度是获得较好的器件特性的重要因素.     

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

Impact of Device Architecture on Performance and Reliability of Deep Submicron SOI MOSFETs (invited paper)

The main electrical properties of advanced Silicon-On-Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitations of submicron MOSFET are comparatively evaluated for various SOI structures. Short channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate length down to sub-0. 1 micron.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Impact of Device Architecture on Performance and Reliability of Deep Submicron SOI MOSFETs (invited paper)

A number of advantages,suitable for many applications,are obtained with the SOIstructure which allows to push back the technological and physical limits intrinsic to thebulk Si structure[1 ,2 ,3] :-the latch-up,a parasitic n-p-n-p str...     

场板SOI RESURF LDMOS表面势场分布解析模型

以往对SOI器件的建模基本上基于漂移区全耗尽的假设,且大多未考虑场板对表面势场分布的影响。通过分区求解二维泊松方程,建立了场板SOI RESURF LDMOS表面电势和表面电场分布解析模型。该模型同时考虑了栅场板和漏场板的作用,既适用于漂移区全耗尽的情况,也适用于漂移区不全耗尽的情况。利用此模型和半导体器件仿真工具Silvaco,详细探讨了器件在不同偏压下栅场板和漏场板对漂移区表面电势和电场分布的影响。解析模型结果与数值仿真结果吻合良好,验证了模型的准确性。     

薄膜全耗尽SOI短沟道MOSFET准二维电流模型

本文在分析薄膜全耗尽SOI器件特殊物理效应的基础上,建立了可细致处理饱和区工作特性的准二维电流模型。该模型包括了场效应载流子迁移率、速度饱和以及短沟道效应等物理效应,可以描述薄膜全耗尽SOI器件所特有的膜厚效应、正背栅耦合(背栅效应)等对器件特性的影响,并且保证了电流、电导及其导数在饱和点的连续性。将模型模拟计算结果与二维器件数值模拟结果进行了对比,在整个工作区域(不考虑载流子碰撞离化的情况下)二者吻合得很好。     

SOI横向栅控双极晶体管特性研究

横向SOI双极技术具有工艺简单、寄生电容小等优势,被认为是射频领域最有希望的技术之一。为了得到可用于射频领域的SOI横向栅控双极晶体管特性,采用一种SOI横向栅控双极晶体管器件结构,研究范围包括工艺实现过程和器件性能特性。实验表明,该器件工艺与平面CMOS工艺完全兼容,通过对栅端电压的控制,可以实现hFE在一个较大的范围内自由调节,具有更大的使用灵活性。     

新型多栅全耗尽SOI器件研究进展

随着器件尺寸的不断缩小,对更大驱动电流和更有效抑制短沟道效应器件的研制成为研究的热点,SOI多栅全耗尽器件由于对沟道更好控制能力能够有效地解决尺寸缩小带来的短沟道效应问题[1].本文主要介绍SOI/MOSFET单栅、平面双栅、FinFET、三栅、环绕栅、G4-FET等新型多栅全耗尽SOI器件的研究进展.     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

SOI结构P型SiGe沟道混合模式晶体管器件模型研究

在带有应变SiGe沟道的SOIMOSFET结构中 ,把栅和衬底相连构成了新型的混合模式晶体管 (SiGeSOIBMHMT) .在SIVACO软件的器件数值模拟基础上 ,对这种结构的P型沟道管工作过程作了分析 ,并建立了数学模型 .提出在低电压 (小于 0 7V)下 ,衬底电极的作用可近似等效成栅 ,然后依据电荷增量 (非平衡过剩载流子 )的方法 ,推导出该结构的I V特性方程 .该方程的计算结果与器件模拟结果相一致.     

沟道热载流子导致的 PDSOI NMOSFET's击穿特性

对热载流子导致的 SIMOX衬底上的部分耗尽 SOI NMOSFET's的栅氧化层击穿进行了系统研究 .对三种典型的热载流子应力条件造成的器件退化进行实验 .根据实验结果 ,研究了沟道热载流子对于 SOI NMOSFET's前沟特性的影响 .提出了预见器件寿命的幂函数关系 ,该关系式可以进行外推 .实验结果表明 ,NMOSFET's的退化是由热空穴从漏端注入氧化层 ,且在靠近漏端被俘获造成的 ,尽管电子的俘获可以加速 NMOSFET's的击穿 .一个 Si原子附近的两个 Si— O键同时断裂 ,导致栅氧化层的破坏性击穿 .提出了沟道热载流子导致氧化层击穿的新物理机制     

Experimental characterisation of PD SOI MOSFET devices fabricated with diamond-shaped body contact

The design of diamond-shaped body-contacted (DSBC) devices using standard layers in a 0.35?µm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process is described in this article. The technology is based on a manufacturable partially depleted SOI process targeted for radio frequency applications. The experimental measurements of drain induced barrier lowering for the fabricated DSBC structure showed suppression of floating body effects (FBE) at the promising rate of 24?mV/V. The measurement results confirmed current drive (I _DS) improvement by 25% at V _DS?=?1.5?V and V _GS?=?1.5?V compared to conventional body-tied-source (BTS) device. A constant and steady output conductance (g _DS) in the saturation region was observed for the DSBC structure. The gate trans-conductance (g _m) is improved by 34% at V _DS?=?1.5?V and V _GS?=?1.5?V compared to conventional BTS device. Three-dimensional device simulation provides insight on FBE suppression and channel current improvement. Experimental results confirmed the area efficiency of the DSBC structure and its excellent current drive performance.     

SOI Technologies Overview for Low-Power Low-Voltage Radio-Frequency Applications

Thanks to their structure, the SOI technologies present several intrinsic advantages for analog and RF applications. Indeed, as it is well established now, these technologies allow the reduction of the power consumption at a given operating frequency. Moreover, the high-insulating properties of SOI substrates, in particular when high resistivity substrate is used, make that these technologies are perfect candidates for mixed-signal applications. In the present paper, we will discuss the performances of the SOI technologies in radio-frequency range. First of all, the high-frequency behavior of SOI substrates, thanks to the characterization of transmission lines, will be shown. The impact of the SOI substrate resistivity on the performances of passive components will also be analyzed. Then, an overview of RF performances of SOI MOSFETs for two different architectures, fully- and partially-depleted, will be achieved and compared to the bulk ones. Finally, the influence of some specific parasitic effects, such as the kink effect, the self-heating effect and the kink-related excess noise, on the RF performances of SOI devices will be studied, thanks to a specific high-frequency characterization.     

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.