Analog/RF Performance of Graded Channel Gate Stack Triple Material Double Gate Strained-Si MOSFET with Fixed Charges

Silicon - The performances of analog/RF parameters of a graded channel gate stack triple material double gate (GCGS-TMDG) strained-Silicon (s-Si) MOSFET with fixed charges are analyzed by using...     

Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions     

Subthreshold Modeling of Graded Channel Double Gate Junctionless FETs

Silicon - In this paper, 2-D analytical models of channel central potential, threshold voltage, subthreshold current and subthreshold swing for graded channel double gate (GC-DG) Junctionless FETs...     

Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications

Silicon - Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes....     

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

Silicon - The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel...     

Performance Analysis of Sub 10 nm Double Gate Circular MOSFET

Silicon - In this work, TCAD based investigation of various Circular double gate MOSFET (CDGT) architectures have been carried for Low-Power(LP) & High- Performance (HP) applications at...     

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Silicon - Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel...     

Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

Silicon - This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current...     

Design Considerations and Capacitance Dependent Parametric Assessment of Gate Metal Engineered SiNW MOSFET for ULSI Switching Applications

Silicon - This work investigates design consideration of Gate Electrode Workfunction Engineered (GEWE) silicon nanowire MOSFET at room temperature. It is perceived from the results that the...     

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

Silicon - The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate...     

Linearity Performance Analysis of Double Gate (DG) VTFET Using HDB for RF Applications

Silicon - In recent low-power electronics industry, Tunnel field-effect transistors (TFETs) have shown the superior performance such as decreased leakage current and lower subthreshold slope (SS)....     

Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications

The Fin shaped Field Effect Transistors (FinFETs), are the front runner of the current sub-nanometer technology node. The semiconductor industry adopts it in high-performance (HP) and low-power (LP) applications due to greater electrostatic control and better scalability. This paper explores the numerically simulation based comparison of bulk and silicon-on-insulator (SOI) technology double gate (DG), triple gate (TG) FinFETs. The essential processing steps required to create the GS high-k dielectric bulk and SOI FinFETs are demonstrated. The electrical performance parameters of the device such as I_on/I_off ratio, subthreshold swing (SS), and drain induced barrier lowering (DIBL) are extracted. Based on the three-dimensional (3D) ATLAS^TM simulation results, TG FinFET shows an ameliorated performance over DG in bulk and SOI technology as well. In order to control the short channel effects (SCEs), gate-stack (GS) high-k dielectrics are introduced with fixed thickness interfacial-layer (IL) and high-k dielectric material in between the gate material and semiconductor. The GS high-k dielectrics suppress the SCEs to large extent in both devices and technologies. The GS SOI FinFETs demonstrates the improved performance over the bulk counterpart and TG FinFET is the best among them. Further, the similar kind of investigation has been carried out for T_fin variations. These devices reveal the excellent control of SCEs when the fin is narrow. The ratio of SOI and bulk TG FinFET I_on/I_off ratio with T_fin variations provide evidence that, the SOI based devices are competent for HP and LP applications.     

A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET

A Double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) is emerging device architecture in sub-nanometer regime. The performance of DG MOSFET can be ameliorated by gate and channel engineering. The concept of graded-channel gate-stack (GCGS) and dual-material (DM) are incorporated in DG MOSFET. A two-dimensional (2D) analytical surface potential model for GCGS DMDG MOSFET is developed based on the solution of Poisson’s equations with appropriate boundary conditions. It has been found that analytically modeled data is in good degree of agreement with numerically simulated data. The combination of both DM and GC concept introduces a step variation in potential profile at the junction of both materials in channel region and ameliorates the short channel effects (SCEs). A suppressed subthreshold swing (SS) and drain induced barrier lowering (DIBL) has been observed in the device due to an elevated average velocity of carrier and reduced drain field effect by the use of DM and GC with GS. Further, analog/RF characteristics such as transconductance generation factor (TGF), cut-off frequency (f_T) and transconductance frequency product (TFP) have been examined with different GS high-k dielectrics. The numerically simulated data has been extracted using 2D ATLAS device simulator.     

Influence of Barrier with Gate Sinking on the Performance of InAs Composite Channel DMDG-HEMT Devices for High-Frequency Applications

Silicon - In this work, the impact of barrier thickness (Tb) on the behavior of InGaAs/InAs/InGaAs composite channel Dual material Double gate (DMDG) high electron mobility transistor (HEMT)...     

A 2-D Analytical Modeling of Dual Work Function Metal Gate MOSFET Using High-K Gate Dielectric with Enhanced RF/Analog Performance for Low Power Applications

A 2-dimensional electrostatic potential modeling of fully depleted channel, with high-k based dual work function double gate (DWFDG) MOSFET, has been devel     

Modified Core-Shell Double Gate Junctionless MOSFET with High ON-State and Low Leakage Currents

Silicon - In this proposed article, an investigation has been studied for low leakage current and high on-state current with heavily doping in source and drain region of Double Gate Junctionless...     

L-Shaped Schottky Barrier MOSFET for High Performance Analog and RF Applications

Silicon - This work presents the design and simulation of a novel double-gate L-shaped Schottky barrier MOSFET (DG-LS-SB-MOSFET). The device uses a low work function metal near source-channel...     

Quantum Analytical Model for Lateral Dual Gate UTBB SOI MOSFET for Analog/RF Performance

Silicon - This paper presents a quantum analytical modeling of UTBB SOIMOSFET as lateral dual gate for the first time. In this paper, a 2-dimensional analytical modeling of electric field...     

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Silicon - This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has...     

An Accurate Model of Threshold Voltage and Effect of High-K Material for Fully Depleted Graded Channel DMDG MOSFET

Silicon - In this study, an accurate model for threshold voltage of graded channel dual material double gate (GCDMDG) structure metal-oxide-semiconductor (MOS) has been established and a...