一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術

一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術被提出, 其藉由大角度離子佈植摻雜物穿透閘極間隙壁. 藉由此技術方法,可使用同一光罩而同時形成淡摻雜區域於閘極間隙壁氧化層下方且形成高摻雜區域,其可於互補式金氧半複晶矽薄膜電晶體製作時簡化製程步驟.更進一步地,藉由此技術,與傳統的單一高濃度摻雜源汲極技術相較,此方法可得到更好的N型及P型薄膜電晶體特性,且無需增加光罩製程.     

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.     

Tenth-micron polysilicon thin-film transistors

Small thin-film polysilicon transistors are of interest for load devices in static random-access memory (SRAM) cells of the near future. We present measured characteristics of thin-film transistors (TFT's) with gate lengths ranging from 7 to 0.12 μm made in large-grain polysilicon     

Use of sacrificial spacers for fabricating LDD transistors in a CMOS process

The use of sacrificial spacers for LDD transistors in a CMOS process is described. LPCVD nitride or PSG is employed as the sidewall-spacer material which is selectively etched off after the LDD's n-/n+ junction formation, thus allowing subsequent shallow p+ implant self-aligning to the polysilicon gate. Deeper n-/n+ junctions with adequate drain/gate overlap for n-channel LDD transistors to minimise hot-electron effects can then be made while simultaneously the shallow p+ junction with high punch-through immunity is preserved for p-channel transistors. The conflicting diffusion requirements in forming n-/n+ and p+ source-drain junction depths are therefore decoupled.     

Superbeta polysilicon emitter transistors

In-situ phosphorus-doped polysilicon emitters deposited on monocrystalline silicon substrates at a temperature of 627°C and subjected to no additional high-temperature annealing are shown to be capable of giving Gummel numbers GEin excess of 10¹⁵scm^-4. Polysilicon emitters formed in this way have been used to produce superbeta transistors with performance comparable to the record levels recently reported for MIS emitter devices. In particular, common-emitter current gains β in excess of 30000 have been obtained at low VCBvalues.     

A novel approach for fabricating light-emitting porous polysilicon films

By etching back the as-oxidized polysilicon using reactive ion, a uniform porous polysilicon structure with significant enhancement of photoluminescence (PL) intensity was formed. We further found that the PL peak is centered at around 680 nm and is independent on the porosities or sizes of Si micropores. These results indicate the light emission in the samples should not be a consequence of the quantum confinement. Instead, the 680-nm peak should be due to the non-bridged oxide hole centers (SiO·) at the oxidized grain boundaries of the polysilicon.     

High-gain SOI polysilicon emitter transistors

The authors report the first high-gain polysilicon emitter bipolar transistors fabricated on zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) material. Current gains as high as 230 were obtained. Polysilicon emitter bipolar transistors made on bulk silicon wafers with identical and simultaneous heat treatments show significant differences in emitter resistance and DC characteristics as compared with SOI bipolar transistors. Post-metal anneal improves the current gain and base current ideality at low base-emitter voltages for both types of wafers     

High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Vertical bipolar transistors in laser-recrystallized polysilicon

Vertical bipolar n-p-n transistors with a base width of 0.2 µm have been fabricated in laser-recrystallized polysilicon films on thermally oxidized silicon substrates. With proper hydrogen annealing steps, common-emitter current gains on the order of 100 were possible. Recombination in the base-emitter space-charge region was found to be the dominant source of base current.     

Current gain in polysilicon emitter transistors

The common-emitter current gain β in a shallow polysilicon emitter transistor is derived by solving the minority-carrier transport equation in the silicon-polysilicon structure. Coupled With the majority-carrier transport, an equation for the current gain is obtained which depends on the physical properties of the polysilicon as well as the silicon emitter and base doping profiles. The calculations are based on the carrier trapping model proposed in the literature and ignore any minority-carrier recombinations. The model predicts the current gain of a polysilicon emitter transistor increases at low current and high temperature and approaches that of a conventional metal contact transistor at high current and low temperature. This is due to the potential barrier across the grain boundaries, while impeding the majority-carrier flow, inject minority carriers as a bias is developed across the grain boundaries. It also predicts a decrease in cutoff frequency fTdue to minority carriers stored in the polysilicon.     

Avalanche-induced effects in polysilicon thin-film transistors

A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices     

Effective recombination velocity of polysilicon contacts for bipolar transistors

The effective surface recombination velocity is determined analytically for a doped polysilicon contact to the emitter of a bipolar transistor in the presence of a thin interfacial oxide layer. Results are presented for various doping levels, oxide thicknesses and barrier heights. The analysis considers both tunnelling and thermionic emission through the interface.     

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.<>     

Floating body effects in polysilicon thin-film transistors

Floating body effects in polycrystalline silicon thin film transistors (poly-TFTs) are investigated by means of numerical simulations. The current increase in the output characteristics at large V_DS, usually referred to as the “kink effect” is explained by impact ionization occurring in the high-field region at the drain end of the channel. Its effect is enhanced by the action of a parasitic bipolar transistor in the back-channel region, whose base current arises from the impact generated holes. The dependence of the kink on the recombination kinetics is also investigated     

Characteristics of p-channel polysilicon conductivity modulatedthin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

基于表面势的多晶硅晶体管漏电流物理模型

提出了一种基于薄层电荷模型、陷阱态密度和表面势的多晶硅薄膜晶体管漏电流物理模型。模型采用非迭代的运算方法, 简单且适用于所有大于平带电压的工作区域。 考虑了包括高斯分布的深能态和指数分布的带尾态在内的陷阱分布形式, 陷阱分布参数的提取通过光电子调制谱方法实现。通过模型与现有实验结果的比较, 得到一致的符合结果。     

Low-temperature process for high-mobility polysilicon TFTs

Thin-film transistors (TFTs) have been realised by a low-temperature (T? 580°C), short process, on polycrystalline silicon thin films deposited by PECVD on glass. Field-effect mobility up to 35cm2V-1s-1 has been measured on such devices.     

On the modeling of polysilicon emitter bipolar transistors

In this paper, an attempt is made to derive a general analytical formulation for the current gain and emitter transit time of a polysilicon emitter bipolar transistor (BJT), which includes all previous models as particular cases. Firstly, it is shown that the minority-carrier injection and storage in the polysilicon region can be simply described by effective values of the minority-carrier diffusion length and mobility. These quantities are precisely defined, and depend on the microscopic transport properties of polysilicon grains and grain boundaries. Secondly, a general expression for the effective recombination velocity relative to the poly/mono interface is derived, which includes, and in some cases extends, all previous approaches. This results in a simple and general formulation which avoids some unnecessary simplification present in nearly all previous treatments, and allows easy comparison of the different models for the poly/mono interface and a clear assessment of the relevance of each physical mechanism. Finally, minority-carrier injection and storage in the single-crystal region is addressed. The effect of oxide breakup on both current gain and emitter transit time is also considered, and different models are compared