双NIOSⅡ软核系统在潮流能发电中的应用

开发海洋潮流能对缓解能源危机具有重要意义,电力变换系统是潮流能发电系统的关键技术之一。提出了一种利用SOPC技术实现潮流能发电电力变换控制系统的设计方法,采用单片高性能FPGA芯片构建双NIOSⅡ软核系统,其中一个NIOSⅡ处理器负责系统任务调度和能量管理,一个NIOSⅡ处理器负责电力变换控制和异常诊断。针对电力变换系统的信息数据特点,提出了基于RAM、FIFO、GPIO的双NIOSⅡ处理器握手机制,并给出了系统的具体设计实现。该双NIOSⅡ处理器系统提高了系统的任务调度灵活性、控制算法处理速度和应急处理能力。     

一种阵列众核处理器的多级指令缓存结构

阵列众核处理器由于其较高的计算性能和能效比已经被广泛应用于高性能计算领域。而要构建未来高性能计算系统处理器必须解决严峻的"访存墙"挑战以及核心协同问题。通常的阵列处理器中,核心多采用单线程结构,以减少开销,但是对访存提出了较高的要求。在阵列众核处理器中,在单核心中引入硬件同时多线程技术,针对实验中一级指令缓存命中率随着线程数增加而显著降低的问题,提出了一种面向阵列众核处理器的冗余指令缓存存储结构,基于该结构,提出采用FIFO及类LRU替换策略。通过上述优化的高速缓存结构设计,经实验模拟,双线程整体指令Cache失效率降低了25.2%,整体CPI性能提升了30.2%。     

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications

Future embedded systems demand multi-processor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semi-automated, time consuming and error prone.In this paper, we present a fully automated design flow to generate communication assist (CA) based multi-processor systems (CA-MPSoC). A worst-case performance model of our CA is proposed so that the performance of the CA-based platform can be analyzed before its implementation. The design flow provides performance estimates and timing guarantees for both hard real-time and soft real-time applications, provided the task to processor mappings are given by the user. The flow automatically generates a super-set hardware that can be used in all use-cases of the applications. The software for each of these use-cases is also generated including the configuration of communication architecture and interfacing with application tasks.CA-MPSoC has been implemented on Xilinx FPGAs for evaluation. Further, it is made available on-line for the benefit of the research community and in this paper, it is used for performance analysis of two real life applications, Sobel and JPEG encoder executing concurrently. The CA-based platform generated by our design flow records a maximum error of 3.4% between analyzed and measured periods. Our tool can also merge use-cases to generate a super-set hardware which accelerates the evaluation of these use-cases. In a case study with six applications, the use-case merging results in a speed up of 18 when compared to the case where each use-case is evaluated individually.     

异构多核系统中跨时钟域的解决方法

随着集成电路的集成度与性能的不断发展,芯片的功耗问题已经变的十分严重,功耗带来的挑战日益突出。异构多核动态调频架构是目前研究低功耗的主流方向。SOC系统当中同一时刻只有一个处理器能够控制总线,其它处理器则处理等待状态,异构多核动态调频架构能够通过降低不控制总线的处理器频率来达到降低功耗的目的。异构多核领域的处理器和总线跨时钟域解决方案,此方案在国内属于首次提出,可以运用在异构多核动态调频(DFS)架构当中。目前手持终端设备越来越强调功耗的重要性,因此异构多核领域的处理器和总线跨时钟域解决方案将有非常好的应用前景。该方案通过在处理器和AMBA总线之间添加FIFO以及一些复杂的算法,达到消除亚稳态和正常通信的目的。最终,通过仿真发现任意调节处理器的工作频率都能满足传输协议。证明该方案能在异构多核动态调频架构中运用。     

ARM7处理器NUC710ADN扩充双网口设计

在ARM7处理器NUC710ADN的第一个网口的基础上,利用网口驱动芯片DM9000AEP扩充了第二个网口,使系统实现双网口通信。给出了硬件设计电路,对DM9000AEP的驱动程序在μClinux下的移植过程进行了描述,测试结果表明双网口都能正常可靠的工作,达到了ARM7处理器进行双网通信的功能要求。     

基于双核处理器的机敏结构振动主动控制器设计

针对分布植入式压电机敏结构振动主动控制技术需求,提出一种新型基于嵌入式架构的多通道振动响应控制器;该系统以嵌入式处理器(ARM)和数字信号处理器(DSP)为双处理器核心,ARM处理器上运行实时操作系统μC/OS-II,并提供人机接口单元和通信等功能,DSP处理器主要负责数据采集、算法运算和处理结果输出,整个系统充分结合了ARM处理器强大的中断处理能力和DSP处理器高效快速的数据处理能力;详细阐述系统总体设计思想、系统软硬件设计方案、系统构成与核心部件、功能指标和开发过程,以及实验测试设置与结果验证;设计开发与测试分析表明,该控制器性能良好且功能丰富,能够满足实际研究工作的需要。     

基于TMS320F2812多种总线的ISA卡设计

针对某型无人机导航/飞控联机调试时多种通信接口的需求,采用DSP处理器、双口RAM和工控PC机的ISA总线来完成CAN,RS422,RS485,TTL232/RS232等多总线接口电路的设计,其结构简单、实用性强。可方便无人机飞控系统的调试和仿真,且可广泛应用到多总线的工控系统中。     

以ARM为核心的嵌入式体感遥控器设计

介绍一种以ARM为核心的嵌入式服务机器人体感遥控器的设计。硬件上,本遥控器采用具有ARM Cortex—M3内核的STM32F103C8T6作为核心处理器,选用ST公司的iNEMO惯性导航模块进行手部姿态的识别,同时还具有LCD显示模块、无线收发模块和电源模块;软件上,采用嵌入式操作系统μC／OS—Ⅱ实现多任务的调度和外围设备的管理。经实验验证,本遥控器具有高稳定性、高实时性、高可靠性、低误码率等优点。     

小型飞行器无线组网系统设计与实现

针对现有小型飞行器组网通信的无线网络标准技术在接入模式、网络延迟和灵活性等方面存在的问题,提出了一种通视条件全空域无线组网的系统架构和方案,完成了相应组网终端的软硬件设计、实现及系统测试验证。方案在网络层采用动态时分多址(TDMA)接入技术,构建低时延的无中心网状网络,使网络节点可动态、快速地接入和退出网络,兼顾了时间敏感数据的实时传输和突发数据的大容量传输;在物理层采用基于频谱感知的自适应跳频通信技术,以保证不受干扰影响的可靠通信,增强了系统的抗干扰和抗截获能力。在组网终端的设计过程中,利用模块化和低功耗处理器集成设计,平衡了SWaP指标,满足了苛刻使用环境条件下的通信距离和数据传输速率等指标需求。系统测试验证表明该组网系统方案可行、性能良好。     

龙芯2号同时多线程处理器的软硬件接口设计

随着生产工艺的提高,芯片上能集成越来越多的晶体管,多线程技术也逐步成为一种主流的处理器体系结构技术,而多线程处理器的软硬件接口也就成为急需解决的问题.在分析同时多线程的软件需求的基础上,提出龙芯2号同时多线程处理器的软硬件接口协同设计解决方案,给出相应的操作系统实现方案.同时,在Linux 2.4.20的基础上实现了龙芯2号同时多线程处理器相应的操作系统.通过运行SPEC CPU2000等测试程序进行性能评测,充分说明实现软硬件接口的龙芯2号同时多线程处理器极大地提高了多进程负载的性能.分析和设计方案不仅适用于同时多线程处理器,而且对于片内多核处理器的设计也有借鉴作用.     

基于STM32嵌入式的无线通信远程数据传输控制系统设计

无线通信远程数据传输控制系统对提高数据传输稳定性起到积极作用,大量数据传输任务给系统的控制功能带来巨大挑战,为此利用STM32嵌入式技术实现无线通信远程数据传输控制系统的优化设计。将STM32芯片以嵌入式的方式安装到数据传输控制器中,改装传输数据处理器,加设时钟发生器。通过系统电路的调整与连接,完成数据传输控制硬件系统的设计。在硬件设备的支持下,采集并处理无线通信数据资源,设置远程数据传输控制协议。在协议约束下,根据信道特征合理分配远程传输数据资源,最终从传输速率、传输流量等方面,实现系统的无线通信远程数据传输控制功能。通过系统测试实验得出结论：在优化设计系统的控制下,远程数据传输速率误差、丢包率控制和传输拥塞总时长均低于预设值,且吞吐率高于88%,由此说明优化设计系统的控制功能和运行性能均满足设计与应用要求。     

波导耦合机器人控制板的研究

研制了一块微操作机器人控制板，采用USB接口通信和C8051单片机做规划器。介绍了PDIUSBD12和C8051F236的内部结构、性能指标，并给出了波导耦合机器人控制系统软硬件和系统结构设计。该控制板在实际工作中运行良好，性能稳定。     

Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.     

基于ARM9处理器的GPS车载导航系统终端

针对传统的车载导航系统终端大多采用单片机为主控处理器,存在处理速度慢,功耗高等问题,提出了采用32位ARM9的嵌入式系统进行控制,研制了新一代的GPS车载导航系统终端。给出了详细的系统硬件电路图,介绍了导航地图的实现。该系统以较少的硬件资源,实现了较高的性能,使得系统具有处理速度快、功耗低、可靠性高等特点。     

Silicon Debug of a PowerPC™ Microprocessor Using Model Checking

When silicon is available, newly designed microprocessors are tested in specially equipped hardware laboratories, where real applications can be run at hardware speeds. However, the large volumes of code being run, plus the limited access to the internal nodes of the chip, make it very difficult to characterize the nature of any failures that occur.In this paper, we describe how temporal logic model checking was used to quickly characterize a design error exhibited during hardware testing of a PowerPC microprocessor. We outline the conditions under which model checking can efficiently characterize such failures, and show how the particular error we detected could have been revealed early in the design cycle, by model checking a short and simple correctness specification. We discuss the implications of this for verification methodologies over the full design cycle.     

Design and performance evaluation of a pixel cache implemented within application-specific integrated circuits

The application-specific integrated circuit (ASIC) design and the performance of a graphics processor that uses a pipelined-cache with FIFO memory to transfer a 3D pixel array and its z values to the frame buffer in one cycle are described in detail. The functional modules in the graphics processor include: (1) a video refresh converter, (2) a module that combines texture-mapped patterns onto Phong-shaded surfaces, and (3) a bidircctional parallel link between external devices and the frame-buffer modules. Digital differential analyzer (DDA) algorithms and the size of the pixel cache relative to the frame-buffer bandwidth, have been selected for good overall performance. A drawing speed of 8 ns/pixel (32 bits/pixel) or 1.2 million Phong-shaded polygons/s (100-pixel polygons, texture mapped with hidden surface removal) was achieved when 60-ns accesstime single port DRAMs and synchronous DRAMs were used.     

Parallel Queue Processor Architecture Based on Produced Order Computation Model

This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a first-in-first-out (FIFO) circular queue-registers instead of random access registers. Datum is inserted in the queue-registers in produced order scheme and can be reused. We show that this feature has profound implications in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed.Our performance evaluations show a significant performance improvement (e.g., 10 to 26% decrease in program size and 6 to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.     

基于指示信号方式实现跨时钟域数据传输的方法

随着片上系统(SoC)技术的发展,芯片内各个模块交流频繁。异步系统因功耗低、速度提升潜力大和抗干扰能力强而备受青睐,但是异步电路设计复杂,数据的跨时钟域传输是亟需解决的问题。国际上目前最流行的方式是FIFO,但随着SoC复杂度的提升,一个系统上集成上百个模块,利用FIFO将会占用大量的资源,产生很大的功耗。通过分析异步传输的特点,提出一种使用指示信号来实现跨时钟域数据传输的方法,该方法与FIFO相比,在性能不减的情况下大大降低了功耗及其复杂度。利用Verilog对两个模块(CPU和FPGA)的跨时钟域数据传输进行设计仿真,通过Xilinx公司的Vivado硬件验证了其可行性。最后通过与FIFO方式的设计进行对比,说明该方法比FIFO具有更好的应用价值。     

一种飞控计算机双核数据通信设计

针对无人机飞控计算机数据传输实时性高、吞吐量大的特点,将双端口RAM芯片CY7C028应用于基于双ARM处理器LPC3250的无人机飞控计算机,实现双处理器间的高速数据通信;通过对CY7C028的详细介绍,给出了CY7C028与LPC3250的硬件电路设计,并在ADS集成开发环境下实现了CY7C028与双处理器的驱动设计;经实验证明,双处理器数据传输速率平均高达5M字节/秒,满足无人机数据传输要求,从而为基于双处理器的嵌入式飞控计算机提供了一种可靠、稳定、高速的数据通信方法。     

Portability in MAC protocol and transceiver software implementations for LR‐WPAN platforms

In a variety of emerging networked computing system domains over the years, there have been bursts of activity on new medium access control (MAC) protocols, as new communication transceiver technologies with greater data‐movement performance or lower power dissipation have been introduced. To enable implementations flexible to evolving standards and improving application‐domain insight, such MAC protocols are typically initially implemented in software, and interface between applications or system software, typically executing on an embedded processor or microcontroller, and the evolving radio transceiver hardware. Many challenges exist in implementing MAC protocols across evolving or competing transceiver hardware implementations and processor architectures. Some of these challenges are peculiar to the requirements of MAC protocols, and others are a result of the plethora of system and processor architectures in the embedded systems domain. This article studies the challenges facing software implementations of MAC protocols running on embedded microcontrollers, and interfacing with radio transceiver hardware. Experience with an implementation of the IEEE 802.15.4 MAC across three hardware platforms with different processor, system, and systems software architectures is presented, focusing on implementation approach and interfaces. Pitfalls are pointed out, and guidelines are provided for ensuring that new MAC implementations are easily portable across processor architectures and transceiver hardware. Copyright © 2010 John Wiley & Sons, Ltd.