北京正负电子对撞机次级束质子单粒子翻转计算和试验研究

北京正负电子对撞机(BEPC)电子直线加速器试验束打靶产生的次级束中包含质子,其中能量约为50MeV~100MeV的质子占有很大比例,这弥补了国内高能质子源的空白。本工作计算得到次级束中的质子能谱,建立质子单粒子翻转截面计算方法,在北京正负电子对撞机次级束质子辐射环境中,计算静态随机存取存储器的质子单粒子翻转截面,设计了SRAM质子单粒子翻转截面测试试验,发现SRAM单粒子翻转和注量有良好的线性,这是SRAM发生单粒子翻转的证据。统计得到不同特征尺寸下SRAM单粒子翻转截面,试验数据与计算结果相符,计算和试验结果表明随着器件特征尺寸的减小器件位单粒子翻转截面减小,但器件容量的增大,翻转截面依然增大,BEPC次级束中的质子束可以开展中高能质子单粒子效应测试。     

SRAM single event upset calculation and test using protons in the secondary beam in the BEPC

The protons in the secondary beam in the Beijing Electron Positron Collider(BEPC) are first analyzed and a large proportion at the energy of 50-100 MeV supply a source gap of high energy protons.In this study, the proton energy spectrum of the secondary beam was obtained and a model for calculating the proton single event upset(SEU) cross section of a static random access memory(SRAM) cell has been presented in the BEPC secondary beam proton radiation environment.The proton SEU cross section for different characteristic dimensions has been calculated.The test of SRAM SEU cross sections has been designed,and a good linear relation between SEUs in SRAM and the fluence was found,which is evidence that an SEU has taken place in the SRAM.The SEU cross sections were measured in SRAM with different dimensions.The test result shows that the SEU cross section per bit will decrease with the decrease of the characteristic dimensions of the device,while the total SEU cross section still increases upon the increase of device capacity.The test data accords with the calculation results,so the high-energy proton SEU test on the proton beam in the BEPC secondary beam could be conducted.     

纳米器件质子在轨单粒子翻转率预计方法

研究了纳米器件在空间轨道中质子引起单粒子翻转(SEU)率的预计方法。以65 nm SRAM为样品,利用加速器进行了质子和重离子单粒子翻转试验,分别基于质子试验数据和重离子试验数据,预计了空间轨道中质子引起的单粒子翻转率。结果表明,用重离子试验数据预计的质子单粒子翻转率比用质子试验数据预计的低1.5个数量级。研究认为,为了评估纳米器件单粒子翻转敏感性,需进行质子单粒子翻转试验,并基于质子试验数据进行在轨质子翻转率预计。     

Single event upset and total dose radiation effects on rad-hard SRAMs

Radiation hardened 16K and 64K CMOS SRAMs were tested at the Brookhaven SEU Test Facility. No failures of 16K SRAMs were observed at room temperature with any value of the feedback resistors. SEU cross section measured at elevated temperatures was a function of reduced feedback resistance. A difference was observed in critical LET forBr andAu ions. SEU cross section decreased at very high angles of incidence. After initial SEU testing, the 64K SRAM was degraded by proton total dose irradiation. An increase in the SEU cross section as well as imprinting of the memory pattern was observed. Test chips fabricated by the same technology were also submitted to proton radiation. Threshold voltage shift was measured for NMOS transistors with and without inversion bias. An increase in the density of interface states for both NMOS and PMOS transistors was measured by the charge-pumping technique. This research has been supported by the NASA grants NAG-5-929 and NAG-9-333.     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

Estimating the Single-Event Upset sensitivity of a memory array using simulation

This paper proposes a straightforward methodology to estimate by simulation the Single-Event Upset (SEU) sensitivity of a memory array using open source and commercial codes. It is based on a four-step process including the calculation of the deposited energy distribution in sensitive volumes, the determination of a criterion for SEU triggering, the count of SEUs, and finally the SEU cross-section calculation. The approach is validated with neutron irradiation experiments performed on a 65 nm Static Random Access Memory (SRAM).     

Experimental research of heavy ion and proton induced single event effects for a Bi-CMOS technology DC/DC converter

This paper tested and analyzed heavy ion and proton induced single event effects (SEE) of a commercial DC/DC converter based on a 600 nm Bi-CMOS technology. Heavy ion induced single event transients (SET) testing has been carried out by using the Beijing HI-13 tandem accelerator at China Institute of Atomic Energy. Proton test has been carried out by using the Canadian TRIUMF proton accelerator. Both SET cross section versus linear energy transfer (LET) and proton energy has been measured. The main study conclusions are: (1) the DC/DC is both sensitive to heavy ion and proton radiations although at a pretty large feature size (600 nm), and threshold LET is about 0.06 MeV·mg/cm²; (2) heavy ion SET saturation cross section is about 5 magnitudes order larger than proton SET saturation cross section, which is consistent with the theory calculation result deduced by the RPP model and the proton nuclear reaction model; (3) on-orbit soft error rate (SER) prediction showed, on GEO orbit, proton induced SERs calculated by the heavy ion derived model are 4-5 times larger than those calculated by proton test data.     

Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Computer simulations with the Spectre circuit simulator from Cadence Design Systems and a proton-accelerator experiment are conducted to investigate the relationship of single-event-upset (SEU) susceptibility to memory-cell layout in the context of a 0.18-μm CMOS SRAM using the dual interlocked storage cell (DICE) technology with differing separations of the pair transistors designed to store a 0 or 1, namely, 0.9 and 2.5 μm, respectively. The simulated values of critical charge for an upset are found to be greater by a factor of 10 for the wider separation. With 1-GeV proton irradiation, using the wider separation of pair transistors is found to reduce the SEU count by a factor of 5.5–15 (depending on the supply voltage). In the experiment, lowering the supply voltage of the memory bank from 1.8 to 0.7 V is found to increase on average the SEU cross section by a factor of 3. Close agreement is observed between the simulated and measured results.     

High performance energy efficient radiation hardened latch for low voltage applications

Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits show a lesser immunity against soft error, because of the smaller device node capacitances in nanoscale technologies and near-threshold voltage operation. Due to these reasons, the tolerance of the sequential circuits to SEUs is an important consideration in nanoscale near threshold CMOS design. This paper presents an energy efficient SEU tolerant latch. The proposed latch improves the SEU tolerance by using a clocked Muller- C and memory elements based restorer circuit. The parasitic extracted simulations using STMicroelectronics 65 nm CMOS technology show that by employing the proposed latch, an average improvement of ∼40% in energy delay product (EDP), is obtained over the recently reported latch. Moreover, the proposed latch is also validated in a TCAD calibrated PTM 32 nm framework and PTM 22 nm CMOS technology nodes. In 32 nm and 22 nm technologies, the proposed latch improves the EDP ∼12% and 59% over existing latches respectively.     

Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of the system. The fault injection is composed of injecting SEUs into user design memory, and used configuration memory of the exploited FPGA. Using the experimental results, the sensitivity of Altera FPGAs to SEU faults are analyzed and derived. The analytical results reveal that the configuration memory is more significant than design memory to the SEUs due to the relative number of SRAM bits. Moreover, in this framework, in the case of injecting SEUs into user memory, the fault injection experiments are accelerated by the cooperation between a simulator and the FPGA.     

An advanced SEU tolerant latch based on error detection

This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the Celement.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5％ less energy and 33.1％ less propagation delay than the triple modular redundancy (TMR) latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively.     

Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators

Evaluation of the single event upsets (SEUs) impact on SRAM-based FPGAs is a major issue in the adoption of these FPGAs in aerospace applications. In this context, different approaches have been recorded in the literatures, among which the emulation methods are applied most frequently regarding their proper cost-effectiveness and time-saving aspects. This paper has proposed a new approach for increasing the SEU emulation rate in the dynamic partial reconfiguration (DPR)-based emulators. Unlike the traditional procedure that emulates the SEU faults only in one loop, the proposed three-level management algorithm (3-LMA) consists of three nested loops. Theoretical analysis and experimental results show that the suggested technique is to some orders of magnitude faster than traditional approach.     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.     

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.     

Proton damage in GaAs solar cells

A simplified model for the short-circuit current reduction caused by proton-induced radiation damage is described. The model accounts for the nonuniformity of defect production within heteroface GaAs shallow junction solar cells. The results from the model show agreement with the strong energy dependence observed in proton radiation damage experiments.     

Pulsations of semiconductor lasers with a proton bombarded segment: Well-developed pulsations

We present an analytic theory of well-developed pulsations in semiconductor lasers with a proton bombarded segment. A rate equation model is used with the proton bombarded region modeled as a fast saturable absorber. We obtain a closed form solution for the pulse shape, width, and energy, as well as the pulsation rate. The pulses can be as short as the diode roundtrip time (∼10 ps). A simple pulsation condition is derived; it agrees with the previously determined small signal instability criterion. Pulsation does not require absorber cross section larger than gain cross section.     

A Built-in Single Event Upsets Detector for Sequential Cells

A built-in single event upsets (SEUs) detector is presented in this paper. This detector utilizes charge sharing to detect an SEU in a sequential cell, and the detection process is analyzed through Accuro simulations in a 65 nm technology. The normal operation of this detector would not induce obvious performance degradation of the target circuit. Through using this detector, error correction can be achieved based on dual modular redundancy (DMR) while the related power is about 20.4 % lower than that induced by triple modular redundancy (TMR).     

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection

The reliability of microprocessors is a big concern in space environments, where they are exposed to cosmic radiation. This radiation can produce Single Event Upsets (SEUs). Some of these microprocessors, often called soft processors, are implemented on SRAM-based FPGAs instead of being manufactured as an ASIC. Fault injection campaigns are needed in order to estimate the soft processor reliability in this harsh environment. This work, characterizes a new RISC soft-core, called lowRISC, based on the RISC-V ISA. Ten tests have been carried out to characterize the SEU sensitivity of lowRISC. Also, we have performed a comparison among lowRISC and other microprocessors, concluding that their sensitivities are all in the same range.     

质子引入的6T SRAM单粒子翻转截面预测模型

提出了一种基于SOI工艺6T SRAM单元质子辐射的单粒子饱和翻转截面的预测模型,该模型通过器件物理来模拟辐照效应,利用版图和工艺参数来预测质子引入的单粒子饱和翻转截面。该模型采用重离子的SPICE测试程序对质子辐射的翻转截面进行预测,该方法简单高效,测试实例表明在0.15μm SOI工艺下,预测的质子引入的单粒子翻转饱和截面和实际测试的翻转截面一致。     

Laser cross section measurement for the evaluation of single-event effects in integrated circuits

The cross section of ICs extracted from particles accelerator testing is extended to the pulsed laser testing. The extraction methodology attached to this new parameter is presented. It provides a new tool for integrated circuits reliability quantification, illustrated in the case of SEU sensitivity evaluation of a single SRAM cell.