A low-power high-performance current-mode multiport SRAM

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-μm CMOS process have shown 2.8 to 9.9× in energy savings and 1.02 to 6.36× reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32×64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach     

High-performance CMOS buffered gate modulation input (BGMI) readoutcircuits for IR FPA

A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit. An experimental 128×128 BGMI readout chip has been designed and fabricated in 0.8 μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip under 77 K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5×10⁷ electrons, the transimpedance of 2.5×10⁹ Ω at 10 nA background current, and the arrive power dissipation of 40 mW. The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved In the BGMI circuit with the pixel size of 50×50 μm². These advantageous characteristics make the BCMI circuit suitable for various IR FPA readout applications with a wide range of background currents     

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A 1.5-V 900-MHz monolithic CMOS fast-switching frequencysynthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm². The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset     

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.     

A quadrature data-dependent DEM algorithm to improve imagerejection of a complex ΣΔ modulator

A dynamic element matching (DEM) algorithm is presented that is controlled by the quadrature output data of a complex sigma-delta modulator. This DEM technique is used to correct the gain and phase errors between the circuits in the in-phase and quadrature-phase feedback paths of the modulator. The key feature of this DEM technique is that it does not cause leakage of high-frequency quantization noise in the signal band, as encounters with the periodic or pseudorandom DEM techniques. No test signal is required to measure the gain and phase errors, and as the DEM circuit is operating continuously, it compensates for changes in, e.g., temperature and supply voltage. A 0.35-μm CMOS prototype chip has been designed to test the DEM circuit. A batch of 38 measured samples shows a typical mismatch-independent image rejection ratio of 63 dB with DEM     

Low-phase-noise LC quadrature VCO using coupled tank resonators ina ring structure

The concept of coupled resonators is employed in a ring VCO structure to reduce the phase noise. This architecture allows the design of low-phase-noise voltage controlled oscillators (VCOs) using integrated low-Q inductors. Quadrature differential outputs are also realized in this design. Two monolithic LC tanks are coupled together to implement a transimpedance resonator with an effective Q close to twice that of a single tank. In addition, the coupled tank's transimpedance resonator provides 90° phase shift. Four such stages are cascaded in a ring structure to provide I-Q differential outputs, and to further reduce the phase noise. A prototype of the VCO is built in a 0.35-μm CMOS technology. The measured phase noise is -122 dBc/Hz at 600-kHz offset from 1.93 GHz. The VCO draws 9.2 mA from a 3-V supply, and occupies a chip area of 1.1×1.1 mm²     

True color 1024×768 microdisplay with analog in-pixelpulsewidth modulation and retinal averaging offset correction

A liquid-crystal-on-silicon microdisplay based on a 1024×768 two-dimensional pixel array fabricated in a digital 0.35-μm CMOS process displays images with a color depth of 8 bits per color. The pixel pitch is 12 μm and the total chip area is 214 mm². Pixel brightness is controlled by modulating the pulsewidth of the pixel voltage drive signal with an in-pixel analog pulsewidth modulation (PWM) circuit which utilizes human optic nerve spatio-temporal averaging to eliminate comparator offset. The 16 million transistor chip displays images at a maximum rate of 85 Hz and has a power dissipation of 200 mW from a single 3.3-V supply     

Low power dynamic circuit for power efficient bit lines

In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory’s bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity.     

A BiCMOS dynamic multiplier using Wallace tree reductionarchitecture and 1.5-V full-swing BiCMOS dynamic logic circuit

The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one     

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valuedMOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54×51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-μm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit     

Bit-line clamped sensing multiplex and accurate high voltagegenerator for quarter-micron flash memories

This paper proposes circuit technologies adaptable to the potential scalability of flash memory cells and an accurate internal voltage generator for use under low voltage operation. A circuit with a relaxed layout pitch, bit-line clamped sensing multiplex, and intermittent burst data transfer (four phases with 500 ns/20 ns) is proposed for a three times feature-size pitch. A 5-μA low-power dynamic band-gap generator with voltage boosted by using triple-well bipolar transistors and voltage-doubler charge pumping, for accurate generation of 10 to 20 V, are also proposed for use at V_vv of under 2.5 V. To demonstrate the circuit feasibility, a 105.9-mm² 128-Mb experimental chip was fabricated using 0.25-μm technology     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

A wideband CMOS sigma-delta modulator with incremental dataweighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-μm CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm². Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance     

A supply-noise-insensitive CMOS PLL with a voltage regulator usingDC-DC capacitive converter

A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-μm 3.3-V standard digital CMOS process and occupies 2.3 mm². The power consumption at 3.3 V including buffer is 42 mW at 500 MHz     

Accurate in situ measurement of peak noise and delay change inducedby interconnect coupling

An accurate in situ noise and delay measurement technique that considers interconnect coupling effects is presented. This paper improves upon previous work by proposing (1) a novel accurate peak detector to measure on-chip crosstalk noise, and (2) in situ measurement structure to characterize the dynamic delay effect. A test chip was fabricated using 0.35-μm process and measured results demonstrate the effectiveness of the proposed technique. Noise peak measurements show 40-60 mV (1.8% average) accuracy to simulation results and dynamic delay change curve match well with SPICE. The proposed measurement technique can be used for interconnect model verification and calibration, and has applications to various design automation tools such as noise-aware static timing analysis     

High-speed low-power direct-coupled complementary push-pull ECLcircuit

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-μm double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit