100 nm超浅结制作工艺研究

在对深亚微米技术的探索中,通过实践,得到了100 nm以下N型高掺杂浓度超浅结的工艺流程。介绍了采用低能量离子注入技术结合快速热退火技术制作超浅结的方法,并对需要考虑的沟道效应及瞬态增强扩散效应进行了机理分析。     

砷预非晶制作结深小于0.25μm的浅结

本文报道了As预非晶制作浅P~+n结,对As预非晶的能量和剂量的选择作了研究,并对常规炉退火(950℃,N_2,30m)和快速热退火(RTA,1050℃,10_s)作了比较。结果表明,A_s预非晶可有效地抑制B~+注入沟道效应,阻止B~+增强扩散,在常规条件下可以实现x_j<0.25μm,R_□<100Ω/□的源漏浅结,并已应用于1M位DRAM生产。     

浅结激光退火的实验研究及工艺模型

随着器件尺寸缩小,浅结、超浅结的制作日益成为重要的工艺模块.对于22 nm及以下技术代来说,除了采用低能离子注入获得极浅的原始注入分布外,通常还采用短时或者瞬时激光退火来激活注入杂质,以保持原始的注入杂质不发生明显的扩散再分布.详细介绍了一台激光退火设备的搭建情况,利用所搭建的激光退火装置进行浅结、超浅结的激光退火实验研究.另一方面,鉴于当前激光退火工艺模型的欠缺,在实验数据的基础上,初步分析和建立了专门针对浅结激光退火处理的工艺模型.     

硅中注入硼的异常扩散

<正> 浅结制备是超大规模集成电路发展的关键技术之一。硅中硼、磷等杂质注入,在退火时发生异常扩散,使浅结的控制困难。异常扩散是一个瞬态快速扩散过程。对于硼,在退火开始时,杂质分布尾部推移极快,随之减慢,恢复正常扩散。这一过程用衰变时间表征。     

硼扩散源及其在半导体器件中的应用

在半导体器件的制造工艺中,向硅衬底中掺以P型或N型杂质形成PN结的时候居多,但是,本文应用的是形成PN结最基本的方法——杂质热扩散法。通常,这种扩散工艺由淀积和推进扩散二个阶段组成。首先,在淀积工艺中,在硅表面形成浅的高浓度杂质扩散区域,紧接着在推进扩散工艺中使结向更深的硅衬底内部浸透,控制表面杂质浓度。可以说,这种杂质浓度的控制和结深的控制左右着器件的性能。进而,这种扩散的好坏受到淀积工艺相当大的影响。因此,本文在说明了淀积工艺中P型杂质硼源概况的同时,着重介绍一下最近Owens-Illinois公司研究的新硼扩散源“硼~(+TM)(以下TM略去)的特点。     

一种抑制单粒子瞬态响应的SiGe HBT工艺加固技术仿真

基于0.13 μm SiGe BiCMOS工艺,开展了无深槽NPN SiGe HBT工艺和器件仿真。模拟了带深P阱SiGe HBT的制备过程、常规电学特性和重离子单粒子效应。该器件与常规器件相比表现出更优的单粒子瞬态(SET)特性,在关态的SET响应峰值下降了80%,在最大特征频率工作点的SET响应峰值下降了27%,瞬态保持时间也大幅减小。使用深N阱和深P阱隔离同时抑制了集电区-衬底结的漂移载流子收集和衬底扩散载流子收集的过程,极大地提高了器件的SET性能。     

DPRM工艺中刻蚀工艺关键参数对N/P型MOS管交界处的影响

短沟道效应对器件性能的影响不可忽略,高k/金属栅极(High-k/Metal Gate,HKMG)器件可以很好地抑制短沟道效应。HKMG器件中金属栅极的制备工艺有前栅极制造工艺和后栅极制造工艺,其中虚拟栅去除(Dummy Poly Removal,DPRM)过程是后栅极制造中一道至关重要的制程。由于P型MOS管和N型MOS管的金属栅极填充材料不同,制造工艺中要先完成一种MOS管金属栅极的制作再进行另一种MOS管金属栅极的制作,DPRM后N型MOS管和P型MOS管交界处的结构形貌会直接影响金属栅极的填充,进而影响器件性能。在电子回旋共振刻蚀等离子体源条件下,探究DPRM工艺中过刻蚀过程的关键参数对NMOS管和PMOS管交界处结构形貌的影响,进而总结出减弱N/P型MOS管交界处侧向凹陷程度的工艺条件。     

具有T型电荷补偿区的横向超结SOILDMOS

非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。     

10keV B~+注入预非晶化Si的剩余缺陷和浅结

<正> 一、问题的提出和实验方法 在低能注入B~+浅结的过程中,沟道效应难以避免。为避免B~+注入的沟道效应,本文采用100keV下5×10~(15)cm~(-2)的Si~(29)注入n-Si<100>进行非晶化处理。继而进行了10keV,1×10~(15)cm~(-2)的B~+注入形成浅结,然后对样品进行快速热退火(RTA)处理,并观察界面缺陷的     

4千兆赫下噪声3.6分贝的硅双极晶体管

随着器件工艺的发展,小信号硅微波晶体管性能有了很大改进,其中比较主要的器件工艺是: 1.1 微米发射极条宽; 2.砷扩散发射极; 3.与浅结结构相容的欧姆接触。由于这些工艺研究的应用,已制作成在4千兆下噪声系数3.6分贝的硅晶体管。     

Metal Silicides: Active elements of ULSI contacts

As device dimensions scale to the 0.1 urn regime, the self-aligned suicide (SALICIDE) contact technology increasingly becomes an integral part of both the ultra-shallow junction and the metal oxide semiconductor field-effect transistor device itself. This paper will discuss the effect of suicide materials and formation processes on suicide stability, junction consumption, the ability to accurately profile shallow junctions, and contact resistance in series with the channel. The use of suicides as diffusion sources (SADS) provides an important pathway toward optimization of suicide technology. Diffusion of boron and arsenic from nearly epitaxial layers of CoSi₂, formed from bilayers of Ti and Co, offer good suicide stability, ultra-shallow, low-leakage junctions, and low contact resistance.     

The behavior of Ni/Au contacts under rapid thermal annealing in GaN device structures

The effect of rapid thermal annealing (RTA) on Ni/Au contacts on P-type GaN was investigated in terms of surface morphology and diffusion depth of metallic species. Ni/Au contacts were evaporated on the P-type 0.5 μm thick top layer of a GaN P/N homojunction. Optical micrographs revealed that the contact morphology degrades when annealed above 800°C for 1 min. At the same time, both Ni and Au atoms strongly diffuse in the P-type layer and even can reach the junction for a 1 min long annealing at 900°C, therefore making the junction structure unoperable. This behavior was evidenced using the Auger voltage contrast (AVC) technique.     

纳米MOS器件中的超浅结和相关离子掺杂新技术的发展

MOS器件特征尺寸进入纳米领域时如何形成超浅结是一个重要的挑战。文中讨论了纳米 MOS器件对超浅结离子束掺杂技术的特殊要求以及发展超浅结的主要途径 ,介绍了目前超浅结离子掺杂新技术的最新发展 ,并对其前景进行了展望。     

Shallow source/drain extensions for deep submicron MOSFETs using spin-on-dopants

Spin-on-dopants and rapid thermal processing have been used to form ultra-shallow n/sup +/-p junctions with metallurgical junction depths as shallow as 12 nm as determined by secondary ion mass spectroscopy. The electrical junction depth and the total charge concentration have been measured in the vicinity of the junction using electron holography and are shown to be consistent with activation efficiencies of 80%. The ultra-shallow junctions have been used as the source and drain contacts of sub-100-nm gate length MOSFETs. From electrical measurements, the authors extract a lateral diffusion length for the source and drains that is comparable to the vertical extent of the n/sup +/-p junctions.     

The influence of Ge-implantation on the electrical characteristicsof the ultra-shallow junction formed by using silicide as a diffusionsource

The electrical characteristics of ultra-shallow p⁺/n junctions formed by implanting a 60 keV Ge⁺ into a TiSi₂ layer have been studied. A very low reverse leakage current density (≅0.4 nA/cm² at -5 V) and a very good forward ideality factor n (≅1.001) were achieved in these ultra-shallow p ⁺/n junctions. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth was measured to be 600 Å and the surface concentration was about 3 times higher than that of the conventional samples     

A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

We have proposed and fabricated a novel 50-nm nMOSFET with side-gates, which induce inversion layers for virtual source/drain extensions (SDE). The 50-nm nMOSFETs show excellent suppression of the short channel effect and reasonable current drivability [subthreshold swing of 86 mV/decade, drain-induced barrier lowering (DIBL) of 112 mV, and maximum transconductance (g/sub m/) of 470 /spl mu/S//spl mu/m at V/sub D/=1.5 V], resulting from the ultra-shallow virtual SDE junction. Since both the main gate and the side-gate give good cut-off characteristics, a possible advantage of this structure in an application to multi-input NAND gates was investigated.     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. I. Theoretical derivation

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-κ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization     

Ultra-thin-base Si bipolar transistor using rapid vapor-phasedirect doping (RVD)

A novel doping method called rapid vapor-phase direct doping (RVD) is developed to form ultra-shallow junctions. The base region of a conventional bipolar transistor is formed by this method, and in ultra-narrow 25-nm base is obtained. The Gummel plot of this device shows almost ideal characteristics. This result suggests that this method does not induce any defects which cause a leakage current. RVD is a thermal diffusion method using hydrogen as a carrier gas and B₂ H₆ as a source gas. In this method, the impurity atoms directly diffuse from the vapor phase into silicon by a rapid thermal process without a boron-glass layer or metallic boron layer. By varying the source gas flow rate, doping time, and temperature, ultra-shallow junctions below 40 nm with controlled surface concentrations are successfully formed. An ultra-shallow 20-nm junction with surface boron concentration of 4×10¹⁸ cm^-3 is obtained at 800°C for 5 min with B₂H₆ flow rate of 30 ml/min     

Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability