High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging

A novel micro-electromechanical system (MEMS) package has been developed based on modular, reconfigurable components such as substrate, cap, bond region and through-wafer electrical interconnect (TWEI). The paper presents the details of the process for the fabrication of high density, high aspect ratio TWEIs that includes deep dry etching holes through the substrate, depositing an insulation layer and depositing a conductive layer. Two different processes to make the TWEI have been developed: Post-Process where the TWEI is fabricated after the fabrication of MEMS devices and Pre-Process where the TWEI is fabricated before the fabrication of MEMS device. For both processes, the interconnect holes are created by an anisotropic etching process-inductively coupled plasma (ICP) etching. For the post-process, a silicon dioxide layer was deposited in a plasma enhanced chemical vapor deposition (PECVD) chamber to insulate the interconnect holes. For the pre-process, the PECVD process was replaced with a thermal oxide growth step to ensure a more conformal oxide coating. Three different ways to deposit a conductive layer after deposition of an insulation layer have been practiced: sputtering Cu, electroplating Cu and low-pressure chemical vapor deposition (LPCVD) of phosphorus doped polysilicon. The electrical performance of the TWEIs achieved in each way was measured, analyzed and discussed.     

Novel multijunction solar cell design for low cost,high concentration systems

In the quest to reduce the levelized cost of energy, recent concentrated photovoltaics innovations have striven to increase the solar cell conversion efficiency. Another approach aims at concentrating more light on the solar cell in order to reduce its share of the energy cost. We propose new cell structures that are tailored for high conversion efficiency at solar concentration exceeding 1000 suns, with a minimum amount of heat generated. These designs are composed of multiple junctions (3, 4, and 5) of materials lattice matched to gallium arsenide (GaAs) with bandgaps at or above that of GaAs. Simulations that include thermal effects and electrical resistance effects are used to predict the performances of the proposed designs under high concentrations. A relative cost analysis shows a reduction in electricity cost when using these designs compared with the state of the art triple‐junction solar cell. Further cost reduction schemes using these proposed designs are discussed. Copyright © 2015 John Wiley & Sons, Ltd.     

Improved reliability of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with high density silicon nitride passivation

We have systematically studied the effects of Si_xN_1 − x passivation density on the reliability of AlGaN/GaN high electron mobility transistors. Upon stressing, devices degrade in two stages, fast-mode degradation and followed by slow-mode degradation. Both degradations can be explained as different stages of pit formation at the gate-edge. Fast-mode degradation is caused by pre-existing oxygen at the Si_xN_1 − x/AlGaN interface. It is not significantly affected by the Si_xN_1 − x density. On the other hand, slow-mode degradation is associated with Si_xN_1 − x degradation. Si_xN_1 − x degrades through electric-field induced oxidation in discrete locations along the gate-edges. The size of these degraded locations ranged from 100 to 300 nm from the gate edge. There are about 16 degraded locations per 100 μm gate-width. In each degraded location, low density nano-globes are formed within the Si_xN_1 − x. Because of the low density of the degraded locations, oxygen can diffuse through these areas and oxidize the AlGaN/GaN to form pits. This slow-mode degradation can be minimized by using high density (ρ = 2.48 g/cm³) Si₃₆N₆₄ as the passivation layer. For slow-mode degradation, the median time to failure of devices with high density passivation is found to increase up to 2× as compared to the low density (ρ = 2.25 g/cm³) Si₄₃N₅₇ passivation. A model based on Johnson-Mehl-Avrami theory is proposed to explain the kinetics of pit formation.     

Graded-channel MOSFET (GCMOSFET) for high performance, low voltageDSP applications

Graded-Channel MOS (GCMOS) VLSI technology has been developed to meet the growing demand for low power and high performance applications. In this paper, it will be shown that, compared to conventional complementary metal-oxide-semiconductor (CMOS), the GCMOS device offers the advantage of significantly higher drive current, capable of lower threshold voltage with improved punchthrough resistance, lower body effect and lower series resistance, thus making it most suitable for applications that require both high performance and low power consumption, such as digital signal processing (DSP). This is demonstrated, for the first time, by much improved low voltage circuit performance of a DSP logic circuit fabricated using a 0.5 μm GCMOS process. At 1.8 V, a 30% speed improvement over CMOS is achieved, and the power-delay product is reduced by 25%. In addition, similar speed improvement is achieved in SRAM's with consistent performance improvement over a wide range of temperatures between -50 and 150°C     

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

A new defect in which a chip "floats" over the board surface after chip placement is appearing in the low-cost, high-throughput flip chip on board (FCOB) assembly that is based on no-flow underfill. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." A process model has been developed that will allow an understanding of the underlying physics of the floating phenomena and identification of process variables so that this process defect can be eliminated. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the theoretical model's predictions.     

Run-length limited (3, 11) code for high density optical storagesystems

A run-length limited (RLL) code for high density optical storage systems is proposed. The minimum and maximum run-length constraints are d=3 and k=11, respectively. The code rate is 2/5, And the resulting density ratio is 1.6, which is larger than that of eight-to-fourteen (EFM) and EFMPlus codes     

High density, low leakage Back-End 3D capacitors for mixed signals applications

ITRS 2018 compliant capacitors have been developed with low-cost anodic Ta₂O₅ material. High capacitance values and very low leakages have been obtained on low thermal budget capacitors fabricated with a CMOS-compatible process. High densities in the order of 10 fF/μm² and very low leakages down to 10⁻⁷ A/cm² at 10 V have been measured electrically. All these features, combined with a high breakdown voltage superior to 37 V and linearity coefficient down to 82 ppm/V, make such capacitors great candidates for both analog precision and decoupling applications.     

Air-stable,high current density,solution-processable,amorphous organic rectifying diodes (ORDs) for low-cost fabrication of flexible passive low frequency RFID tags

We report on long-term air-stable organic rectifying diodes (ORD) on flexible substrates based on a solution deposited amorphous organic semiconductor (OSC) material, consisting of a co-polymer of arylamine and a fused aromatic species, reaching charge-carrier mobilities of μ = 0.05 cm²/V s (space charge limited current region) and current densities of up to 100 A/cm² at 10 V levels with rectification ratios of 10⁴ operating in the 10 kHz range. The ORDs exhibit a high degree of air-stability without any passivation with extremely reliable reproducibility. ORDs were fabricated on polyethylene naphthalate foils in a vertical sandwich structure with gold and aluminium as the injecting and blocking electrodes respectively via evaporation with the OSC spin-coated in between (Type1). In order to improve device performance of the ORDs, poly(ethylenedioxythiophene):poly(styrenesulfonate) was μ-dispensed as a hole-injection layer (Type2). The results for Type1-diodes show a really narrow spread of the diode characteristics, whereas for Type2 diodes the spread is slightly more but still acceptable. These ORDs prove themselves better than conventional pentacene diodes both in terms of reliability/repeatability of the diode performance and air-stability without an encapsulation layer, and goes towards the enabling of a viable and reliable low-cost fabrication method of radio frequency identification-tags using organic semiconductors.     

High temperature reliability of aluminium wire-bonds to thin film, thick film and low temperature co-fired ceramic (LTCC) substrate metallization

Reliable interconnects are essential for microelectronic systems intended for long life times in harsh environment applications. Intermetallic growth accelerates as the temperature increases, and the material system must be carefully selected to avoid mechanically and/or electrically weak connections. The dominating chip metallization is aluminium, and aluminium wire-bonding is therefore recommended to obtain a mono-metallic system at chip level. A suitable substrate metallization compatible with aluminium wire-bonds at high temperatures (HT) should therefore be found.Test substrates with low temperature co-fired ceramic (LTCC) silver conductors plated with nickel/gold, gold and aluminium thin film, gold thick film, and silver thick film plated with copper/nickel/gold have been manufactured. Wedge/wedge aluminium wire-bonding were performed with 25 μm aluminium wire on the substrates before they were subjected to long term ageing at temperatures up to 250 °C for 6-12 months. Bond-pull strength and electrical resistance were measured during ageing on selected components.The present work shows that long term reliable aluminium wire-bonds for 250 °C operation is feasible both with thin film, thick film and LTCC substrate technology. For the screen-printed conductors, a plating system with nickel is necessary. Aluminium wire bonded to gold thin film displays reliable long term high temperature performance for gold thicknesses up to ∼1 μm.     

High yield manufacture of very low threshold, high reliability, 1.30-µm buried heterostructure laser diodes grown by metal organic chemical vapor deposition

We report the fabrication of very low threshold buried heterostructure lasers by a two-step MOCVD technique. We show very high yield of fabrication, very high uniformity of the initial characteristics, good reproducibility, and low degradation rate during the aging test.     

Influence of halogen-free compound and lead-free solder paste on on-board reliability of green CSP (chip scale package)

In the past few years, many studies have reported on the formula of solder metal alloy materials. This paper discusses the influence of organic materials characters, the decomposing rate of flux in lead-free solder paste and coefficients of thermal expansion (CTE) of halogen-free mold compounds during the on-board reliability test, and the failure mechanism in both 63Sn/37Pb and Sn–3.5Ag–0.5Cu lead-free solder balls was reported.The thermal decomposing behavior of flux in the solder paste induced voids in solder joints was examined by thermo-gravimetric analysis (TGA) and X-ray perspective, respectively. On-board temperature cycle test (TCT) reliability failed specimens were sectioned and analyzed by the optical microscope (OM) and X-ray. The evolutions of package warpage change of two kinds of potential halogen-free compounds during the TCT reliability process were monitored by specially designed thermal mechanic analysis (TMA) experiments.The experimental results show that higher IR-reflow peak temperature induced voids forming in the solder joints and then failure mode change from interface between intermetallic and solder to cracks cut across the big voids during TCT test, worse TCT reliability performance ensued. Moreover, according to on-board reliability testing data show that the compound with larger package warpage change generated larger cumulate plastic work in solder joint that caused early failure during TCT process.     

Benzocyclobutene (BCB) dielectrics for the fabrication of high density,thin film multichip modules

A new class of organic dielectrics, benzocyclobutenes, 1, are described and their application to the fabrication of thin film multichip modules is detailed. Key properties for3, a siloxy containing BCB derivative include low dielectric constant (2.7), low loss (0.008 at 1 MHz), low water absorption (0.25% after 24 h water boil) and high degree of planarization (>90% from one layer coverage). All other properties meet the requirements necessary for fabrication of thin film MCM structures.     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

Metal deposition for optoelectronic devices using a low vacuum vapor phase deposition (VPD) system

A vapor phase deposition (VPD) system has been used to deposit magnesium and zinc films and prepare optoelectronic devices under low vacuum conditions, i.e. 1 torr. An analysis of the metal films via SEM, AFM, XRD and four-point probe resistivity measurements revealed comparable characteristics to metal films deposited in a vacuum thermal evaporation (VTE) system. Magnesium cathodes were fabricated for organic light emitting diodes (OLEDs) and organic photovoltaic (OPV) devices. OLEDs were fully made in either the VPD or VTE system employing aluminum tris-(8 hydroxyquinoline) [Alq₃] as the green fluorescent emitter or fac-tris(2-phenylpyridine)iridium [Ir(ppy)₃] as the green emitting phosphor. Analysis of the OLED devices made in the VPD system showed external quantum efficiencies (EQE = 0.9 ± 0.1%) and (EQE = 7.6 ± 0.6%) at a luminance of 100 cd/m² for the fluorescent and phosphorescent devices, respectively. In addition, organic photovoltaics (OPVs) were fully fabricated by both methods employing copper phthalocyanine (CuPc) and C₆₀ as the donor/acceptor materials. Analysis of the OPV devices made in the VPD system showed a power efficiency of 0.5 ± 0.1%, an open circuit voltage of 0.45 ± 0.05% and a fill factor of 0.50 ± 0.05%.     

Coreless printed circuit board (PCB) transformers with high power density and high efficiency

The authors report the use of a coreless printed circuit board transformer for power conversion with very high power density and efficiency. A coreless PCB transformer with an outermost radius of /spl sim/1 cm and 19 turns for both the primary and secondary windings can transfer 19 W at an efficiency of 90%, resulting in a record power density of 24 W/cm/sup 2/. The power density and energy efficiency of a coreless PCB transformer are higher than those of core-based microtransformers. Coreless transformers are simpler in structure, easier to implement in silicon wafer and cheaper than core-based planar transformers.     

Platinum chemical mechanical polishing (CMP) characteristics for high density ferroelectric memory applications

The key component of ferroelectric random access memory (FeRAM) is a capacitor including a ferroelectric thin film and electrode materials. Platinum is one of the suitable metals which meet requirements such as low resistivity, high thermal stability, and good oxygen resistance. Generally, the ferroelectric and the electrode materials were patterned by a plasma etching process. The application possibility of chemical mechanical polishing (CMP) processes to the patterning of ferroelectric thin film instead of plasma etching was investigated in our previous study for improvement of an angled sidewall which prevents the densification of FeRAM. In this study, the characteristics of platinum CMP for FeRAM applications were also investigated by an approach as bottom electrode materials of ferroelectric material in CMP patterning. The removal rate was increased from 24.81 nm/min by the only alumina slurry (0.0 wt% of H₂O₂ oxidizer) to 113.59 nm/min at 10.0 wt% of H₂O₂ oxidizer. Electrochemical study of platinum and alumina slurry with various concentrations of H₂O₂ was performed in order to investigate the change of the removal rate. The decreased particle size in the alumina slurry with an addition of 10.0 wt% H₂O₂ oxidizer made the improved surface roughness of the platinum thin films. Micro-scratches were observed in all polished samples.     

Knowledge, abilities, cognitive characteristics and behavioral competences of engineers with high capacity for engineering systems thinking (CEST)

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