Actel推出首款混合信号FPGA

Actel公司宣布推出首个混合信号FPGA产品系列——Actel Fusion融合可编程系统芯片(PSC),可立即供货。Actel Fusion器件在单片可编程系统芯片中集成了混合信号模拟电路、Flash内存和FPGA架构,让设计人员迅速从概念步向完整的设计,并向市场推出功能丰富的系统。Actel Fusion可编程系统芯片为这些应用领域带来可编程逻辑的优势,应用领域包括电源管理、智能电池充电、时钟生成和管理及电机控制等,而这     

艾默生实现上海赛科联合装置

Actel公司推出全新的Fusion融合技术．开展可编程系统芯片的新纪元。建基于其以Flash为基础FPGA技术的领导地位．Actel现成功开发业界首项为混合式信号解决方案带来真正可编程功能的崭新技术。融合技术率先将混合信号的模拟功能和Flash内存及FPGA结构集成于单片可编程系统芯片中。     

Actel推出首款使用简便的混合信号FPGA器件

Actel公司宣布推出全面的设计环境，作为系统开发新时代的一项重要元素，全力支持最新的Fusion融合可编程系统芯片（PSC）的实施。Actel的Fusion可编程系统芯片与ACtel Libero7．0集成设计环境ODE）结合，可在单芯片上实现前所未有的数字逻辑、模拟功能、嵌入式Flash内存和FPGA架构的集成。Aetel广泛的工具组合将为设计人员带来所需的开发环境、方法和途径，以便轻易地生成、配嚣和校验这项突破性的混合信号FPGA技术。Actel对流行的Libero集成设计环境进行升级可让用户在易用及简单“选与点”（Pick—and—Click）操作的用户界面上完全生成可编程系统芯片；至于低成本的Actel融合启动套件则保证设计能迅速和有效地从构想以至完全实施。     

Actel公司推出Fusion融合技术

Actel 公司宣布推出全新的Fusion融合技术，开展可编程系统芯片的新纪元。基于其以Flash为基础FPGA技术的领导地位，Actel现成功开发出为混合式信号解决方案带来真正可编程功能的崭新技术。融合技术率先将混合信号的模拟功能和Flash内存及FPGA结构集成于单片可编程系统芯片中。     

Actel的FUSION可编程系统芯片获创新大奖

<正>Actel公司宣布业界首款混合信号现场可编程门阵列 (FPGA)——Actel Fusion(tm)可编程系统芯片(PSC) 荣获EDN杂志颁发2005年度数字IC和可编程逻辑类别的创新大奖。屡获殊荣的Actel Fusion PSC能前所未有地将混合     

最新可编程平台一览

Actel公司推出全新的Fusion融合技术，为混合式信号解决方案带来可编程能力。此融合技术将混合信号的模拟功能和Flash内存FPGA结构集成于单一可编程系统芯片中。与此同时，当此融合技术与Actel基于Actel基于ARM7和8051的软MCU内核共用时，可作为理想的软处理器平台。这项新技术能发挥Actel以Flash为基础FPGA的独特优势，包括高绝缘性、三井结构以及支持高压晶体管的能力，以满足混合信号系统设计的严格要求。     

可编辑器件——混合信号FPGA

Actel公司推出混合信号FPGA产品系列Actel Fusion融合可编程系统芯片（PSC），Actel Fusion器件住单片可编程系统芯片中集成了混合信号模拟电路、Flash内存和FPGA架构，应用领域包括电源管理、智能电池充电、     

Actel混合信号FPGA拓展可编程系统应用

通信、消费类、工业、医疗等电子产品的功能不断增多，系统的成本压力也随之增加，这给系统设计工程师带来了许多挑战。具有多种功能和高集成度，以降低系统成本的方案，已经成为多数设计人员的首选。在这一方面，Altera的SoPC以及Cypress的PSoC解决方案较为突出。在FPGA方面具有诸多优势的Actel也已经开始关注可编程系统芯片（PSC）市场，并于近期推出了混合信号FPGA解决方案一——Fusion。     

Actel强化可编程系统芯片性能简化嵌入式设计

Actel公司的Fusion器件是一个具有 ARM7功能的单芯片可编程系统芯片(PSC)平台。Actel Fusion PSC将业界标准的ARM7技术与混合信号FPGA相结合,将众多功能集成到单一芯片中,包括支持 ／-12V模拟I／O、高达 8Mbit嵌入式Flash内存、集成ADC和高达150     

40nm FPGA的功耗管理和优势

随着工艺尺寸的减小,数字逻辑电路的漏电流成为当前FPGA面临的主要挑战.静态功耗增大的主要原因是各种漏电流源的增加.图1所示为随着更小逻辑门长度的技术实现,这些漏电流源是怎样随之增加的.此外,如果不采取专门的功耗措施,较大的逻辑电容和较高的开关频率也会导致动态功耗增大.     

A novel FPGA architecture supporting wide, shallow memories

This paper investigates an architecture designed to implement wide, shallow memories on a field programmable gate array (FPGA). In the proposed architecture, existing configuration memory normally used to control the connectivity pattern of the FPGA is made user accessible. Typically, not all the switch blocks in an FPGA are used to transport signals. By adding only a modest amount of circuitry, the configuration memory in these unused switch blocks (or unused paths within used switch blocks) can be used to implement wide, shallow buffers and other similar memory structures. The size of FPGA required to implement a benchmark circuit that makes use of the wide, shallow memories, is 20% smaller than a standard memory architecture. In addition, the benchmark circuit is on average 40% faster using the proposed architecture.     

基于FPGA的多通道模拟信号源设计

针对航天测试领域对模拟信号源的设计要求,提出一种新的信号源实现方法。该方法借助计算机软件能实时编程生成波形数据,通过对波形重构电路,调理电路和多通道电路的合理设计,由FPGA控制逻辑实现波形重构和多通道输出。由于方波信号沿变时具有的特殊性,设计专门的方波产生电路,通过实验验证,对原先设计电路的阻尼特性加以改进,实现了方波信号高精度的可靠输出,满足技术指标要求。目前,该信号源已广泛应用于多项航天测试项目。     

面向对称体系结构的FPGA仿真模型研究

缓慢的软件模拟器给体系结构研究带来了极大不便,FPGA硬件仿真的模拟速度很快,但仿真系统的规模严重受限于FPGA的容量.较大规模的体系结构系统仿真采用多片FPGA互连,不仅增加了设计的复杂性,也增加成本.因此提出一种面向对称体系结构的FPGA仿真模型.经仿真系统评估,其仿真系统能够增大FPGA芯片的仿真规模,减少仿真系统对FPGA资源的需求,有效支持在有限的FPGA资源上进行大规模对称体系结构仿真研究.     

基于FPGA和ARM架构的OTDR方案

为开发实用便携的嵌入式OTDR(光时域反射仪),文章提出了一种采用FPGA(现场可编程门阵列)进行数据采集和累加平均等简单处理、ARM(精简指令集处理器)进行人机交互和数据分析的设计方案。介绍了该系统的工作原理、硬件设计和软件设计,并对其中FPGA程序进行了重点阐述。实验结果表明,此设计方案融合了两种芯片的特性和优势,系统性能获得了较大提升。     

基于FPGA的雷达视频融合设计

显示雷达视频是雷达显示终端的主要任务,本文介绍了一种视频融合的设计,采用stratixⅡ公司的可编程逻辑器件EP2S30F484C4及QuartusⅡ5.1开发系统实现。由于采用该器件,减少了设备体积,同时也使设备的可靠性和设计的灵活性大大提高。     

An analog architecture on parameter estimation of ARMA models

An analog architecture that is suitable for parameter estimation of autoregressive moving average (ARMA) models is proposed. The convergence theorem that connects this architecture with ARMA parameter estimation is presented. Simulation results indicate that its convergence takes only a few microseconds. Hence, this architecture can lead to online implementations     

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.     

The effect of logic block architecture on FPGA performance

This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay     

Automatic synthesis of FPGA channel architecture for routabilityand performance

This paper considers automatic synthesis of segmented channel architecture of row-based FPGA's so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A channel architecture synthesis algorithm based on simulated annealing has been developed which enhances channel routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance. Excellent results have been obtained for a set of benchmark examples and industrial designs