几种Si、Ge纳米线导热系数的原子模拟

采用非平衡分子动力学方法模拟了Si纳米线、Ge纳米线、核-壳结构的Si/Ge纳米线及超晶格结构的Si/Ge纳米线的导热系数,给出了纳米线的温度与导热系数关系曲线,对比了几种纳米线导热特性的差异,研究结果表明,随着温度的升高,各纳米线的导热系数降低;相同温度下,纳米线导热系数的大小顺序为：核-壳结构的Si/Ge纳米线、超晶格结构的Si/Ge纳米线、Si纳米线、Ge纳米线。     

Thermal and tensile properties of Si/Ge core-shell and superlattice nanowires

The Stillinger-Weber potential-based MD (Molecular dynamics) method is used to simulate the heating-up and axial tension of Si/Ge core-shell and superlattice nanowires; according to the simulative results, the differences in their thermal and mechanical properties are discussed. The results show the following: (1) The Si/Ge superlattice nanowire is more thermally stable than the core-shell one, and their melting points are 1160 and 1320 K, respectively. (2) The Si/Ge core-shell nanowire has higher elastic module than the super-lattice one. (3) Under tension, the super-lattice nanowire has better antideformation capability than the core-shell one but has comparative antiloading capability.     

Thermal and tensile properties of Si/Ge core-shell and superlattice nanowires

The Stillinger-Weber potential-based MD (Molecular dynamics) method is used to simulate the heating-up and axial tension of Si/Ge core-shell and superlattice nanowires; according to the simulative results, the differences in their thermal and mechanical properties are discussed. The results show the following: (1) The Si/Ge superlattice nanowire is more thermally stable than the core-shell one, and their melting points are 1160 and 1320 K, respectively. (2) The Si/Ge core-shell nanowire has higher elastic module than the super-lattice one. (3) Under tension, the super-lattice nanowire has better antideformation capability than the core-shell one but has comparative antiloading capability.     

Phonon Transport of Rough Si/Ge Superlattice Nanotubes

Nanostructuring of thermoelectric materials bears promise for manipulating physical parameters to improve the energy conversion efficiency of thermoelectrics. In this paper the thermal transport in Si/Ge superlattice nanotubes is investigated by performing nonequilibrium molecular dynamics simulations aiming at realizing low thermal conductivity by surface roughening. Our calculations revealed that the thermal conductivity of Si/Ge superlattice nanotubes depends nonmonotonically on periodic length and increases as the wall thickness increases. However, the thermal conductivity is not sensitive to the inner diameters due to the strong surface scattering at thin wall thickness. In addition, introducing roughness onto the superlattice nanotubes surface can destroy the phonon tunneling in superlattice nanotubes, which results in thermal conductivity even surpassing amorphous limit. Furthermore, a nonmonotonic dependence of the thermal conductivity of rough Si/Ge superlattice nanotubes with thicker wall thickness is found, while for thinner wall the thermal conductivity of rough Si/Ge superlattice nanotubes decreases monotonically with surface roughness increasing. Our results provide guidance for designing high performance thermoelectrics using superlattice nanotube.     

Performance analysis of a Ge/Si core/shell nanowire field-effect transistor

We ana/lyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp3d5s* tight-binding treatment of the electronic structure. Comparison of the measured performance of the device with the effects of series resistance removed to the simulated result assuming ballistic transport shows that the experimental device operates between 60 and 85% of the ballistic limit. For this approximately 15 nm diameter Ge nanowire, we also find that 14-18 modes are occupied at room temperature under ON-current conditions with ION/IOFF = 100. To observe true one-dimensional transport in a 110 Ge nanowire transistor, the nanowire diameter would have to be less than about 5 nm. The methodology described here should prove useful for analyzing and comparing on a common basis nanowire transistors of various materials and structures.     

Misfit-guided self-organization of anticorrelated ge quantum dot arrays on si nanowires

Misfit-strain guided growth of periodic quantum dot (QD) arrays in planar thin film epitaxy has been a popular nanostructure fabrication method. Engineering misfit-guided QD growth on a nanoscale substrate such as the small curvature surface of a nanowire represents a new approach to self-organized nanostructure preparation. Perhaps more profoundly, the periodic stress underlying each QD and the resulting modulation of electro-optical properties inside the nanowire backbone promise to provide a new platform for novel mechano-electronic, thermoelectronic, and optoelectronic devices. Herein, we report a first experimental demonstration of self-organized and self-limited growth of coherent, periodic Ge QDs on a one-dimensional Si nanowire substrate. Systematic characterizations reveal several distinctively different modes of Ge QD ordering on the Si nanowire substrate depending on the core diameter. In particular, Ge QD arrays on Si nanowires of around 20 nm diameter predominantly exhibit an anticorrelated pattern whose wavelength agrees with theoretical predictions. The correlated pattern can be attributed to propagation and correlation of misfit strain across the diameter of the thin nanowire substrate. The QD array growth is self-limited as the wavelength of the QDs remains unchanged even after prolonged Ge deposition. Furthermore, we demonstrate a direct kinetic transformation from a uniform Ge shell layer to discrete QD arrays by a postgrowth annealing process.     

Nanostructure design for drastic reduction of thermal conductivity while preserving high electrical conductivity

The design and fabrication of nanostructured materials to control both thermal and electrical properties are demonstrated for high-performance thermoelectric conversion. We have focused on silicon (Si) because it is an environmentally friendly and ubiquitous element. High bulk thermal conductivity of Si limits its potential as a thermoelectric material. The thermal conductivity of Si has been reduced by introducing grains, or wires, yet a further reduction is required while retaining a high electrical conductivity. We have designed two different nanostructures for this purpose. One structure is connected Si nanodots (NDs) with the same crystal orientation. The phonons scattering at the interfaces of these NDs occurred and it depended on the ND size. As a result of phonon scattering, the thermal conductivity of this nanostructured material was below/close to the amorphous limit. The other structure is Si films containing epitaxially grown Ge NDs. The Si layer imparted high electrical conductivity, while the Ge NDs served as phonon scattering bodies reducing thermal conductivity drastically. This work gives a methodology for the independent control of electron and phonon transport using nanostructured materials. This can bring the realization of thermoelectric Si-based materials that are compatible with large scale integrated circuit processing technologies.     

Enhancement of thermoelectric properties by modulation-doping in silicon germanium alloy nanocomposites

Modulation-doping was theoretically proposed and experimentally proved to be effective in increasing the power factor of nanocomposites (Si(80)Ge(20))(70)(Si(100)B(5))(30) by increasing the carrier mobility but not the figure-of-merit (ZT) due to the increased thermal conductivity. Here we report an alternative materials design, using alloy Si(70)Ge(30) instead of Si as the nanoparticles and Si(95)Ge(5) as the matrix, to increase the power factor but not the thermal conductivity, leading to a ZT of 1.3 ± 0.1 at 900 °C.     

Diameter-dependent composition of vapor-liquid-solid grown Si(1-x)Ge(x) nanowires

Diameter-dependent compositions of Si(1-x)Ge(x) nanowires grown by a vapor-liquid-solid mechanism using SiH(4) and GeH(4) precursors are studied by transmission electron microscopy and X-ray energy dispersive spectroscopy. For the growth conditions studied, the Ge concentration in Si(1-x)Ge(x) nanowires shows a strong dependence on nanowire diameter, with the Ge concentration decreasing with decreasing nanowire diameter below approximately 50 nm. The size-dependent nature of Ge concentration in Si(1-x)Ge(x) NWs is strongly suggestive of Gibbs-Thomson effects and highlights another important phenomenon in nanowire growth.     

硼掺杂球磨SiGe合金的热电性能

SiGe合金热电材料作为一种传统的高温热电材料一直以来受到广泛关注。本研究通过B在球磨SiGe合金中的P型掺杂,有效增加了材料的载流子浓度,优化材料的电学性能。通过球磨降低材料的晶粒尺寸,增强晶界对声子的散射,降低材料的晶格热导率。另外,B掺杂使点缺陷散射和载流子-声子散射得到增强,材料的晶格热导率进一步降低。在室温时,Si_(0.8)Ge_(0.2)B_(0.04)的晶格热导率为~4Wm~(-1) K~(-1)。由于掺杂后电导率提高,热导率降低,因此热电优值zT得到了提高。在850K时,Si_(0.8)Ge_(0.2)B_(0.04)的最大热电优值为0.42,与Si_(0.8)Ge_(0.2)B_(0.002)的样品相比,其优值提高了2.5倍左右。     

Diffusion in Si(x)Ge(1-x)/Si nanowire heterostructures

Si0.48Ge0.52/Si tip/nanowire heterostructures were grown by pulsed laser vaporization (PLV) at a growth temperature of 1100 degrees C. Ge diffusion in [111]-growth Si nanowires was studied for different post-synthesis annealing temperatures from 200 degrees C to 800 degrees C. Ge composition profiles were quantified by energy-dispersive X-ray spectroscopy in a transmission electron microscope. The compositional profiles were modeled by a limited-source diffusion model to extract temperature-dependent diffusion coefficients. The Ge diffusion coefficients followed an Arrhenius relationship with an activation energy of 0.622 +/- 0.050 eV. This rather low activation energy barrier is similar to the previously reported activation energy barrier of 0.67 eV for Ge surface diffusion on Si, suggesting that surface diffusion may dominate in nanowires at this length scale.     

Solid State Synthesis and Thermoelectric Properties of Mg-Si-Ge System

1.IntroductionMuch attention has been paid to thermoelectric mate-rials for manufacturing thermoelectric energy conversiondevices by utilizing temperature change from waste heatand geothermal sources[1~5].The performance of ther-moelectric materials is usually expressed by the figure ofmerit z,z=α2σ/k,whereαis the Seebeck coefficient,σis the electrical conductivity and k is the thermal con-ductivity.The higher the z,the higher the effectivenessof a material for thermoelectric applications[…     

Anisotropic thermal conductivity of Ge quantum-dot and symmetrically strained Si/Ge superlattices

We report the first experimental results on the temperature dependent in-plane and cross-plane thermal conductivities of a symmetrically strained Si/Ge superlattice and a Ge quantum-dot superlattice measured by the two-wire 3 omega method. The measured thermal conductivity values are highly anisotropic and are significantly reduced compared to the bulk thermal conductivity of the structures. The results can be explained by using heat transport models based on the Boltzmann transport equation with partially diffusive scattering of the phonons at the superlattice interfaces.     

Selective growth of Ge nanowires by low-temperature thermal evaporation

High-quality single-crystalline Ge nanowires with electrical properties comparable to those of bulk Ge have been synthesized by vapor-liquid-solid growth using Au growth seeds on SiO(2)/Si(100) substrates and evaporation from solid Ge powder in a low-temperature process at crucible temperatures down to 700?°C. High nanowire growth rates at these low source temperatures have been identified as being due to sublimation of GeO from substantial amounts of GeO(2) on the powder. The Ge nanowire synthesis from GeO is highly selective at our substrate temperatures (420-500?°C), i.e., occurs only on Au vapor-liquid-solid growth seeds. For growth of nanowires of 10-20?μm length on Au particles, an upper bound of 0.5?nm Ge deposition was determined in areas of bare SiO(2)/Si substrate without Au nanoparticles.     

Electrical transport of bottom-up grown single-crystal Si(1-x)Ge(x) nanowire

In this work, we fabricated an Si(1-x)Ge(x) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) by using bottom-up grown single-crystal Si(1-x)Ge(x) NWs integrated with HfO(2) gate dielectric, TaN/Ta gate electrode and Pd Schottky source/drain electrodes, and investigated the electrical transport properties of Si(1-x)Ge(x) NWs. It is found that both undoped and phosphorus-doped Si(1-x)Ge(x) NW MOSFETs exhibit p-MOS operation while enhanced performance of higher I(on)～100?nA and I(on)/I(off)～10(5) are achieved from phosphorus-doped Si(1-x)Ge(x) NWs, which can be attributed to the reduction of the effective Schottky barrier height (SBH). Further improvement in gate control with a subthreshold slope of 142?mV?dec(-1) was obtained by reducing HfO(2) gate dielectric thickness. A comprehensive study on SBH between the Si(1-x)Ge(x) NW channel and Pd source/drain shows that a doped Si(1-x)Ge(x) NW has a lower effective SBH due to a thinner depletion width at the junction and the gate oxide thickness has negligible effect on effective SBH.     

Interface charge induced p-type characteristics of aligned Si(1-x)Gex nanowires

This study reports the electrical transport characteristics of Si(1-x)Gex (x=0-0.3) nanowires. Nanowires with diameters of 50-100 nm were grown on Si substrates. The valence band spectra from the nanowires indicate that energy band gap modulation is readily achievable using the Ge content. The structural characterization showed that the native oxide of the Si(1-x)Gex nanowires was dominated by SiO2; however, the interfaces between the nanowire and the SiO2 layer consisted of a mixture of Si and Ge oxides. The electrical characterization of a nanowire field effect transistor showed p-type behavior in all Si(1-x)Gex compositions due to the Ge-O and Si-O-Ge bonds at the interface and, accordingly, the accumulation of holes in the level filled with electrons. The interfacial bonds also dominate the mobility and on- and off-current ratio. The large interfacial area of the nanowire, together with the trapped negative interface charge, creates an appearance of p-type characteristics in the Si(1-x)Gex alloy system. Surface or interface structural control, as well as compositional modulation, would be critical in realizing high-performance Si(1-x)Gex nanowire devices.     

Single-crystalline Ni2Ge/Ge/Ni2Ge nanowire heterostructure transistors

In this study, we report on the formation of a single-crystalline Ni(2)Ge/Ge/Ni(2)Ge nanowire heterostructure and its field effect characteristics by controlled reaction between a supercritical fluid-liquid-solid (SFLS) synthesized Ge nanowire and Ni metal contacts. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) studies reveal a wide temperature range to convert the Ge nanowire to single-crystalline Ni(2)Ge by a thermal diffusion process. The maximum current density of the fully germanide Ni(2)Ge nanowires exceeds 3.5 × 10(7) A cm(-2), and the resistivity is about 88 μΩ cm. The in situ reaction examined by TEM shows atomically sharp interfaces for the Ni(2)Ge/Ge/Ni(2)Ge heterostructure. The interface epitaxial relationships are determined to be [Formula: see text] and [Formula: see text]. Back-gate field effect transistors (FETs) were also fabricated using this low resistivity Ni(2)Ge as source/drain contacts. Electrical measurements show a good p-type FET behavior with an on/off ratio over 10(3) and a one order of magnitude improvement in hole mobility from that of SFLS-synthesized Ge nanowire.     

Transport modulation in Ge/Si core/shell nanowires through controlled synthesis of doped Si shells

Appropriately controlling the properties of the Si shell in Ge/Si core/shell nanowires permits not only passivation of the Ge surface states, but also introduces new interface phenomena, thereby enabling novel nanoelectronics concepts. Here, we report a rational synthesis of Ge/Si core/shell nanowires with doped Si shells. We demonstrate that the morphology and thickness of Si shells can be controlled for different dopant types by tuning the growth parameters during synthesis. We also present distinctly different electrical characteristics that arise from nanowire field-effect transistors fabricated using the synthesized Ge/Si core/shell nanowires with different shell morphologies. Furthermore, a clear transition in the modification of device characteristics is observed for crystalline shell nanowires following removal of the shell using a unique trimming process of successive native oxide formation/etching. Our results demonstrate that the preferred transport path through the nanowire structure can be modulated by appropriately tuning the growth conditions.     

Chemical control of semiconductor nanowire kinking and superstructure

We show that methylgermane (GeH(3)CH(3)) can induce a transition from 111 to 110 oriented growth during the vapor-liquid-solid synthesis of Ge nanowires. This hydride-based chemistry is subsequently leveraged to rationally fabricate kinking superstructures based on combinations of 111 and 110 segments. The addition of GeH(3)CH(3) also eliminates sidewall tapering and enables Ge nanowire growth at temperatures exceeding 475 °C, which greatly expands the process window and opens new avenues to create Si/Ge heterostructures.     

Molecular dynamics simulation of the thermal conductivities of Si nanowires with various roughnesses

Molecular dynamics (MD) simulations were employed to study the heat transfer in a single crystalline Si nanowire with length smaller than phonon mean free path. Thermal conductivity was calculated using a non-equilibrium method that formed a temperature gradient. The effect of varying roughness sizes and direction on the thermal conductivity at room temperature was studied. It was found that the thermal conductivities were reduced as the size of the roughness increased. Furthermore, variations of the thermal conductivities were more prominent with the perpendicular axis roughness than with the parallel axis roughness. The maximum variation was approximately 63% between smooth and rough models with the same wire size. In addition, the mixed size roughness did not reduce thermal conductivity.