基于改进FFT算法的OFDM调制/解调模块设计

文章对传统FFT算法进行了改进,改进后的算法将N点DFT分解成二维√N点DFT的组合,在结构上更适合于用流水线方式实现FFT.文章首先对算法进行了推导,然后基于该算法设计了一个64点、32位字长的定点IFFT/FFT模块,用于802.11a中OFDM的调制/解调.与传统的流水线FFT比较,该模块中的复数乘法运算全部采用移位相加操作完成,因而消除了乘法器及旋转因子ROM的使用,降低了功耗.最后,对该模块进行了验证仿真.结果表明,在流水线饱和的情况下,该模块完成一个64点的FFT运算只需要8个时钟周期,在20MHZ时钟频率下,该模块的功耗为0.26W,完全能满足移动通信中对于高速度、低功耗的要求.     

基于FPGA的FFT处理器设计

针对快速傅里叶变换（FFT）算法的结构和特点,提出了一种基于现场可编程门阵列（FPGA）设计FFT运算的方案。该方案采用基2算法以及单元结构的设计思路,对FFT处理器合理模块化,用VHDL语言对各个模块编程,并在Quartusll软件环境下综合仿真,时序分析结果与Matlab计算结果相一致验证了设计的正确性。FFT与FPGA相结合提高了运算速度,扩大了FFT的应用领域。     

基于FPGA的高速流水线FFT算法实现

提出了在FPGA（现场可编程门阵列）上实现1024点基4-FFT（快速傅里叶变换）算法的设计方案。方案对FFT算法的核心单元即蝶形运算单元的结构进行了分析和优化,用一个复乘器通过时序控制实现了和3个复乘器同样的效率,而且对整个算法的流程采用了流水线式的工作控制方式,不仅节省了FFT在FPGA上实现时占用的硬件资源,并且极大地提高了算法的运算效率。最后给出了仿真实验结果,并同MATLAB的FFT运算结果进行了对比。结果显示,在100MHz时钟条件下,本方案完成1024点的基4．FFT运算仅需51．28μs,完全满足高速FFT运算的实时性要求。     

一种低复杂度的通用FFT处理器

利用R22SDF算法的低复杂度的特点,在其基础上演变出一种通用的FFT算法.该方法可适用于所有的2n点FFT运算.该算法采用流水线结构,以满足数据实时性处理的要求.     

基于CORDIC旋转器的基-3 FFT算法高效设计

设计出一种可以用于FPGA高效实现的基-3 FFT算法,采用改进的三端前馈延迟转换器结构,优化了延迟和运算过程。针对蝶形运算中复数乘法器占据大量内存的问题,引入了CORDIC旋转器实现输入与旋转因子相乘的运算,可以降低乘法运算的复杂度,该CORDIC旋转器采用改进的高基CORDIC算法,解决了传统的CORDIC算法迭代次数多、延迟大的问题,从而达到高吞吐率要求。该基-3 FFT算法以寻址变序、流水处理的方式,可以满足最高运行频率为404 MHz的FFT处理要求。与基于传统复数乘法器的基-3 FFT算法相比,基于CORDIC旋转器的基-3 FFT算法使功耗平均减少了22%,使总延迟平均减少了29%。     

长度为2^n的FFT运算基实现

大点数FFT运算是数字信号处理中关键技术环节,本文提出一种大点数FFT运算基的实现,该实现是根据[1]中所提出的算法,结合寄存器阵列模块和重排序模块,实现FFT运算基模块内部的数据传输和模式切换,以基4与基2为模块中的基本运算单元构成大点数的FFT运算基,在控制电路配合下实现快速傅里叶变换。该实现通过面向寄存器级的Simulink仿真模型,验证本文所设计模块功能的正确性和可行性,为基于大点数的FFT运算指出了一种实现方法。     

DMB-T系统中FFT模块的设计与实现

介绍了地面数字多媒体/电视广播传播系统(DMB-T)中3 780点FFT模块的重要作用.考虑到不适合直接利用现已成熟的基-2和基-4的算法,提出一种全并行流水结构的3 780点FFT的设计和实现方案.该方案采用WFTA算法和PFA算法,把3780分解为7×9×5×4×3共5级的流水线结构.通过对整个系统的仿真与硬件实现,证明该方案性能上能够满足TDS-OFDM系统的信噪比要求.     

FDM调制解调中高速（I）FFT硬件设计

提出了一种64点，512点和1024点（I）FFT（（逆）快速傅里叶变换）的硬件实现方法，适合应用在正交频分复用（OFDM）系统中，实现时采用了16位精度的复数来表示输入输出数据。该算法在运算过程去除了所有的乘法器在运算过程中没有使用乘法器，使得运算速度得到较大地提高。     

基于FPGA的新型高速FFT算法研究与实现

提出一种新型基8/4FFT算法及其实现结构,设计出高速的处理模块.该设计可选择性地实现8 k、4 k及2 k点FFT;通过乘法器的复用,有效降低硬件消耗;应用对称乒乓RAM结构提高了蝶型运算单元的连续运算能力.模块利用Verilog语言进行描述,在Quartus5.0软件环境中完成输入、综合及布局布线.结果表明本文提出的算法结构具有优越的精度和速度,充分能够满足实际应用要求.     

利用近似核与近似取模法改进的Rife算法

为了满足侦察雷达接收机对正弦信号频率实时估计的要求,提出了一种利用近似核和近似取模方法改进的Rife算法.该算法利用4点近似核FFT代替全精度FFT,消除了乘法运算;利用近似取模算法避免了乘法运算和开方运算,整体上使运算量大幅下降.仿真结果显示,该算法保持了全频段高精度测频特性,均方根误差与克拉美罗下界(CRLB)保持...     

高速64点FFT芯片设计技术

针对高速64点FFT(快速傅里叶变换)处理芯片的实现,分析了FFT运算原理,并根据FFT算法原理介绍了改进的FFT运算流图。介绍了FFT处理器系统的各模块的功能划分,并根据FFT处理器结构及其特殊寻址方式,采用Verilog HDL对处理器系统的控制器、双数据缓存、地址生成器、蝶形运算单元以及I/O控制等模块进行了RTL(寄存器传输级)设计,并在ModelSim中对各模块以及整个系统进行功能仿真和验证,给出了部分关键模块的仿真波形图。设计中,注重从硬件实现以及电路的可综合性等角度进行RTL电路设计,以确保得到与期望性能相符的硬件电路。     

一种高效的FFT处理器地址快速生成方法

地址产生器是FFT处理器的主要组成部分,地址快速生成和旋转因子读取次数是它的两个重要指标,但很少有算法能够将其统一起来。本文采取了一种新的操作数地址生成顺序并构造了一种新的FFT循环级数表示方法,基于操作数地址的位倒序方式,提出了一种兼有地址简单快速生成与避免重复读取旋转因子特点的可变长地址生成方法,解决了以往地址产生时生成速度与旋转因子重复读取之间的矛盾,实现了快速和降低系统功耗的统一。     

A Low‐Complexity 128‐Point Mixed‐Radix FFT Processor for MB‐OFDM UWB Systems

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency‐division multiplexing ultra‐wideband systems. The proposed 128‐point FFT processor employs both a modified radix‐2⁴ algorithm and a radix‐2³ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure‐sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware‐ efficient 128‐point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128‐point mixed‐radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128‐point FFT architectures.     

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2^k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm². The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.     

Computationally efficient algorithms for cyclic spectral analysis

Two computationally efficient algorithms for digital cyclic spectral analysis, the FFT accumulation method (FAM) and the strip spectral correlation algorithm (SSCA), are developed from a series of modifications on a simple time smoothing algorithm. The signal processing, computational, and structural attributes of time smoothing algorithms are presented with emphasis on the FAM and SSCA. As a vehicle for examining the algorithms the problem of estimating the cyclic cross spectrum of two complex-valued sequences is considered. Simplifications of the resulting expressions to special cases of the cross cyclic spectrum of two complex-valued sequences, such as the cyclic spectrum of a single real-valued sequence, are easily found. Computational and structural simplifications arising from the specialization are described     

基于FPGA的FFT处理器的设计与实现

对FFT处理器的实现算法-频域抽取基4算法做了介绍。介绍一种以FPGA作为设计载体,设计和实现一套集成于FPGA内部的FFT处理器的方法和设计过程。FFT处理器的硬件试验结果表明该处理器的运算结果正确,并且具有较高运算速度。该方法具有设计简单灵活,体积小等优点,可用于雷达处理、高速图像处理和数字通信等应用场合。     

频谱估计算法在炮口初速测量雷达工程的实现

雷达信号频率参数的测量结果决定了测速雷达的精度。介绍了两种频率估计方法,并应用FFT、MUSIC和ESPRIT算法对高斯白噪声下的多普勒速度进行了估计。通过结果分析,比较了在不同条件下,几种算法的估计精度。结果表明,在信号一定信噪比条件下,采用MUSIC、ESPRIT算法能够实现高精度频率估计。     

Design of an FFT/IFFT Processor for MIMO OFDM Systems

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum² , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements     

Pipeline interleaving design for FIR, IIR, and FFT array processors

In this paper, a floating point multiply- and-accumulate (FMAC) processor capable of running the FIR, IIR, and FFT algorithms is proposed. This processor executes many independent FMAC operations circularly without causing any hazard. The algorithmic processing is decomposed into independent subprocesses, each of which executes a FMAC group and all of the subprocesses are activated in turn. The projection method of VLSI array processors is used to map the data flow of FIR, IIR, and FFT into subprocesses so that the algorithms can be successfully executed by the processor in the way of pipeline interleaving. Because of the 100% utilization of pipeline, a very good performance is achieved.     

Comments on "A 64-point Fourier transform chip for video motion compensation using phase correlation"

For the original paper see ibid., vol. 31, no. 11, p. 1751-61 (Nov. 1996). The commenter states that the fast Fourier transform (FFT) processor of the aforementioned paper by C.C. Hui et al., contains many interesting and novel features. However, it is pointed out that bit reversed input/output FFT algorithms, matrix transposers, and bit reversers have been noted in the literature. In addition, lower radix algorithms can be modified to be made computationally equivalent to higher radix algorithms. Many FFT ideas, including those of the above paper, can also be applied to other important algorithms and architectures.