MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.     

一种单材料双功函数栅MOSFET解析模型

An analytical surface potential model for the single material double work function gate(SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering(DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.     

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device V_th is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.     

Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs

Using a novel HfLaO gate dielectric for nMOSFETs with different La composition, we report for the first time that TaN (or HfN) effective metal gate work function can be tuned from Si mid-gap to the conduction band to fit the requirement of nMOSFETs. This is explained by the change of interface states and Fermi pinning level by adding La into HfO/sub 2/. The superior performances of the nMOSFETs compared with those using pure HfO/sub 2/ gate dielectric are also reported, in terms of higher crystallization temperature and higher drive current I/sub d/ without sacrifice of very low gate leakage current, i.e. 5-6 orders reduction compared with SiO/sub 2/ at the same equivalent oxide thickness of /spl sim/1.2-1.8 nm.     

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.     

Dual work function metal gate CMOS transistors by Ni-Tiinterdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO ₂ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current     

Dual work function metal gate CMOS technology using metalinterdiffusion

In this letter, we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve low threshold voltages for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not disturb the delicate thin gate dielectric and preserves its uniformity and integrity. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively     

Oxygen incorporation in TiN for metal gate work function tuning with a replacement gate integration approach

In this study, we used oxygen to increase the work function of a TiN gated stack. To prevent the EOT growth associated with oxygen incorporation, we proposed a novel replacement gate flow, where oxygen incorporation by O₂ anneal on a thin TiN layer was performed after dopant activation. With this novel flow, a maximum work function tuning range of ∼0.32 eV was achieved without significant EOT penalty, making it attractive for p-type metal gate integration.     

A metal/polysilicon damascene gate technology for RF power LDMOSFETs

This letter describes a metal/polysilicon damascene gate technology for RF power LDMOSFETs. We compare the performance of SOI LDMOSFETs with metal/polysilicon damascene gates to that of identical devices with n/sup +/ polysilicon gates. The gate sheet resistance of the metal/polysilicon gate was 0.2 /spl Omega//sq. This very low sheet resistance greatly improved f/sub max/ and peak PAE, especially for the wide gate fingers that are critical in RF power applications. With a 140 /spl mu/m gate finger width, f/sub max/ was improved from 5 GHz to 25 GHz, and peak PAE at 1.9 GHz was improved from 12% to 52%.     

Dual work function metal gates using full nickel silicidation of doped poly-Si

This paper investigates the work function adjustment on fully silicided (FUSI) NiSi metal gates for dual-gate CMOS, and how it is effected by the poly-Si dopants. By comparing FUSI on As-, B-, and undoped poly-Si using the same p-Si substrates, it is shown that both As and B influence the work function of NiSi FUSI gate significantly, with As showing more effects than B possibly due to more As pile-up at the NiSi-SiO/sub 2/ interface. No degradations on the underlying gate dielectrics are observed in terms of interface state density (D/sub it/), fixed oxide charges, leakage current, and breakdown voltage, suggesting that NiSi FUSI is compatible with dual-gate CMOS processing.     

Work function tuning of fully silicided NiSi metal gates using a TiN capping layer

This paper investigates a new way of tuning the work function of fully silicided (FUSI) NiSi metal gates for dual-gate CMOS using a TiN capping layer on Ni to control the poly-Si dopant distribution during FUSI formation. In addition, by comparing the work function change of NiSi FUSI with and without TiN capping, we provide clear evidence that dopants at the gate electrode and dielectric interface are responsible for the work function change. The TiN capping layer causes no degradation to the underlying gate dielectric in terms of fixed-oxide charge, gate leakage current, and time-dependent dielectric breakdown characteristics.     

Modulation of the effective work function of TiN metal gate for PMOS application

It is important to find a way to modulate the work function of TiN metal gate towards the valence band edge of Si,which can meet the lower threshold voltage requirement of p-type metal-oxide-semiconductor（MOS） transistor.In this work,effects of TiN thickness,post-deposition annealing（PDA）,oxygen incorporation and N concentration variation on the work function of TiN metal gate in MOS structures are systematically investigated. It can be found that the work function positively shifts at the initial stage as the thickness of the TiN layer increases and stabilizes at such a thickness.PDA at N₂ ambience with a trace of O₂ can also cause a positive shift in the work function of TiN metal gate.The same tendency can be observed when oxygen is incorporated into TiN.Finally, increasing the N concentration in TiN can also positively shift the work function.All these measures are effective in modulating the TiN metal gate so that it is more suitable for PMOS application.     

Application of combinatorial methodologies for work function engineering of metal gate/high-κ advanced gate stacks

This paper uses combinatorial methodologies to investigate the effect of TaN-AlN metal gate electrode composition on the work function, for (TaN-AlN)/Hf-Si-O/SiO₂/Si capacitors. We demonstrate the efficacy of the combinatorial technique by plotting work function for more than thirty Ta_1-xAl_xN_y compositions, with x varying from 0.05 to 0.50. The work function is shown to continuously decrease, from about 4.9 to about 4.7 eV, over this range. Over the same range, oxide fixed charge is seen to go from about -2.5 × 10¹² cm⁻³ to about zero. The work functions reported here are about 0.1 eV higher than in a previous study, but are still about 0.2 eV smaller than required for PMOS device applications.     

A physical model for boron penetration through thin gate oxidesfrom p+ polysilicon gates

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation     

针对PMOS应用的TiN金属栅功函数调节

PMOS管需要金属栅的功函数接近硅的价带边,所以寻找到合适的方法调节TiN的功函数使之正向移动是金属栅工程的重点,也是难点。本文详细研究了TiN金属栅的厚度,栅介质沉积后退火,氧引入,以及N含量变化对TiN功函数的影响。发现随着TiN的厚度变厚,功函数会正向移动,但是在某一个厚度会达到饱和,另外,在少量氧气氛围下的栅介质沉积后退火,也能使功函数正向移动,而在TiN中引入氧元素,以及增大N的含量都会使TiN的功函数正向漂移。以上所述方法都能有效的调节TiN的功函数来适应PMOS的需要。     

Tunable oxide-bypassed trench gate MOSFET: breaking the ideal superjunction MOSFET performance line at equal column width

The superjunction (SJ) MOSFET power device is recognized for its higher blocking capability and lower on-state resistance that break the conventional unipolar silicon limit. However, SJ devices below 100 V rating incur the constraint of unrealistically narrow column widths , and their performance is greatly handicapped due to difficulties in the formation of perfectly charge-balanced SJ p-n columns by current process technology. Based on an alternative approach of the tunable oxide-bypassed (TOB) SJ MOSFET concept, a TOB-UMOS device of 79 V rating has been successfully fabricated for the first time. Laboratory measurements indicate that the device breaks the ideal SJ MOSFET performance line at equal column width of 3.5 /spl mu/m, and potentially the ideal silicon limit as well.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R/sub B/ was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 /spl mu//spl Omega//spl middot/cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced f/sub T//f/sub MAX/ values of 41/42 GHz were demonstrated for 0.5/spl times/10/spl mu/m/sup 2/ transistors.     

Control of boron diffusion in polysilicon for constructing overlapping polysilicon gate charge-coupled devices

The diffusion coefficient of boron having values significantly different in silicon and silicon dioxide has been used to control the doping of boron impurity in intrinsic polysilicon deposited over the gate oxide. The method reduces the possibility of doping gate oxide while diffusing boron in polysilicon. Using the method, silicon gate p-MOSFETS and twenty bit photo-sensor, four phase, double overlapping polysilicon gate surface channel charge-coupled devices have been constructed with a transfer efficiency of 0.9990. The measured values of the threshold voltage of MOSFETS are in close agreement with their corresponding calculated values.     

Characterization of Ni/Ho and Ni/Er fully silicided metal gates on SiO2 gate dielectric

This paper investigates the effects of Ho and Er on the sheet resistance and crystallinity of Ni(Ho) and Ni(Er) silicides, the work function (WF) modulation of Ni(Ho) and Ni(Er) fully silicided (FUSI) gate electrodes on SiO₂ dielectric, and the FUSI gated SiO₂/Si interface trap properties by using high-frequency capacitance-voltage (C-V) and photonic high-frequency C-V measurements. It was found that as the thickness percentage of rare earth (RE) metal in the Ni(Ho) or Ni(Er) increases, the sheet resistance of the silicide increases. The crystallinity decreases in the Ni(Ho) and Ni(Er) silicides, and the crystallinity decreases as the Ho thickness percentage increases. As the thickness percentage of Ho in the Ni(Ho) increases from 13% to 30%, the flatband voltage (V_FB) shift increases from −0.19 to −0.27 V. The V_FB shifts negatively 0.17 V due to 10% Er incorporation in the Ni(Er). The V_FB shift can be attributed to the effective WF decrease which may be due to the crystallinity decrease of Ni(Ho) and Ni(Er) FUSI. The interface trap density D_it calculated from the photonic high-frequency C-V curves is in good agreement with that calculated from the high-frequency and photonic high-frequency C-V curves. The Ho or Er addition does not increase the D_it.