Single- and dual-polarized millimeter-wave slot-ring antennas

Single- and dual-polarized dielectric lens-supported slot-ring antennas have been developed for operation at millimeter-wave frequencies. The antennas are fed with a coplanar waveguide (CPW) to be compatible with uniplanar mixers and low-noise amplifiers, and the feedline is shown to have a minimal effect on the antenna performance. The measured antenna patterns agree well with theoretical results and have symmetric main beams, low sidelobe levels (<-15 dB), low cross polarization (<-20 dB), and 27 dB directivity. A 2×2 array of single-polarized slot-ring antennas for monopulse applications demonstrates excellent patterns at 94 GHz with -3 dB crossover power levels in both elevation and azimuth scans. The dual-polarized slot ring antenna patterns are nearly identical to those of the single-polarized antenna, and two-port isolation is as low as -25 dB. The dielectric lens-supported slot-ring antenna is an excellent candidate for compact, low-cost millimeter-wave systems with fixed or variable polarization capabilities     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

Design issues of a low power wideband frequency doubler implementation in 0.18 μm CMOS

This paper presents design issues of a wideband, low power implementation of a frequency doubler (FD) in a commercial 0.18 μm CMOS process. The FD consists of two identical unbalanced source-coupled pairs with different width-to-length (W/L) ratios, whose inputs are connected in parallel and its output is taken single-ended. Amplitude and phase mismatch at the differential input are considered and it is shown that there is minimal effect on the output amplitude of the 2nd harmonic for a 5 dB difference in input amplitude and a 45° difference in phase. Under matched conditions, the implemented frequency doubler can be operated at a supply voltage as low as 1 V, which corresponded to a power consumption of less than 1 mW, has a 3 dB output bandwidth of 4 GHz and a conversion gain of 2.5 dB. At a supply voltage of 1.2 V, the frequency doubler consumed 1.32 mW, has a 3 dB output bandwidth of 3 GHz and a conversion gain of 5 dB. The phase niose degradation is 6 dB in both cases.     

Monolithic implementation of air-filled rectangular coaxial line

An air-filled rectangular coaxial line has been monolithically fabricated. Coaxial line is a suitable structure for reducing the coupling between two close transmission lines. Over the measurement range (from 4 to 38 GHz), the fabricated coaxial line has very low attenuation (<0.08 dB/mm) and low return loss (<-33 dB). The isolation between the two close lines separated by 40 μm is below -43 dB with 1 mm coupling length     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

Sidelobe reduction for a microstrip travelling-wave antenna array using partially random weighting

The sidelobe performance of a microstrip travelling-wave antenna array is limited by the crosspolarised lobes produced if a comb-line is used with a large range of stub widths.1.2 The amplitude taper which can be applied is thereby limited to ?6?7.5 dB, so that very low sidelobes (< ?30 dB) cannot readily be achieved. Here a technique is described which offers copolar sidelobe reduction without excessive crosspolarisation, with calculated sidelobes <30 dB for a 32-element array. An amplitude taper of 20 dB is achieved using a split comb-line (giving 12?15 dB taper) plus partially random weighting.     

N×N optical switch based on cascaded microring resonators

An N×N optical switch based on cascaded microring resonators on chip is proposed. As an example, the 4×4 optical switch is further investigated. It is successfully demonstrated that its insertion loss is relatively low as 2.2 dB, the crosstalk is negligible, and the extinction ratio (ER) is as large as 130 dB. Thermal tuning is employed to make the microrings be in resonance or not, which leads to a response time of several hundred microseconds. Alternatively, doping the desired waveguide regions with p-type or n-type dopants is able to achieve a better response time of several nanoseconds. The proposed design is easily integrated to a large scale with less microring resonators, which ensures the compact size and the low power consumption.     

S波段单片四位数控移相器

描述了Ｓ波段单片四位数字移相器的电路设计、工艺制作和性能。采用集总元件的高通／低通网络构成移相网络和ＧａＡｓＭＥＳＦＥＴ作为开关控制器件,利用南京电子器件研究所标准的离子注入微波单片集成电路（ＭＭＩＣ）制造工艺,研制出Ｓ波段单片四位数字移相器。该移相器在设计工作频带内１６个移相态具有移相精度高（均方根误差小于１°）、输入输出驻波好（＜１．４）和较低的插入损耗（＜５．５ｄＢ）与插损变化（均方根误差小于０．２ｄＢ）等优良的电特性。芯片尺寸为６．４５ｍｍ×１．４ｍｍ×０．２ｍｍ。     

Uniform and high-performance eight-channel bent waveguide SOA arrayfor hybrid PICs

A uniform and high performance eight-channel spot-size-converter integrated SOA (SSC-SOA) array for optical switching gate applications is demonstrated. Bow-shaped waveguides are used to achieve high gain and high ON-OFF ratio switching. All channels of the fabricated eight-channel array show a high fiber-to-fiber gain of 12.7 dB, low polarization-dependent gain (PDG) of <0.5 dB, and a high ON-OFF ratio of >50 dB at a low drive current of 40 mA     

ND:YAG light source and external modulator for a VSB-AM video transmitter: A performance evaluation

A miniature Nd:YAG laser and an intensity modulator based VSB-AM video signal transmitter are described. With a light source having RIN level below -170 dB/Hz, the system allows a relatively low modulation index to be used. For a 40 channel system using a standard MZ, a CTB = 60 dB corresponds to m_i = 1 per cent. With a 75 mW Nd:YAG laser source, a system with a power budget of 5.5 dB and 50 dB CNR is realizable. Several promising techniques of modulator linearization are also given.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Super low noise C-band PHEMT MMIC low noise amplifier with minimuminput matching network

A two-stage PHEMT MMIC low noise amplifier with a very low noise figure as low as 0.76 dB and gain >16 dB at 5.4 GHz has been implemented using a minimum input matching network. It is believed that the noise figure of 0.76 dB is the best result ever reported to date from MMIC LNAs over this frequency range. This is attributed to the low noise performance of the PHEMT transistor and minimised parasitic resistance of the input matching network     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as g_m-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than ? 9.58 dB while output return loss has less than ? 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm².

     

Ku-band RF MEMS tunable comb line band reject filter on coplanar transmission line

A band reject filter with tuning capability is presented on a CPW transmission line on silicon substrate using comb line and RF MEMS variable capacitor, enabling compatibility with planar IC technology. A conventional CPW on a substrate consists of a central strip conductor with semi-infinite ground planes on either side. A comb line is etched on the signal line of the CPW and the MEMS bridge capacitor is put on the same line in shunt. Tunability of the filter is achieved by putting the MEMS bridge in either up or down state. The rejection at the centre frequency of stop bands are around ?40.24 dB for down state and ?38.21 dB for up state of the bridge. A low insertion loss, as low as ?0.68 dB, is obtained in the pass band. The proposed device structure is simulated using ANSOFT HFSS v13^® for RF analysis and COVENTORWARE (2008)^® for mechanical and electromechanical characterization, both static and transient analysis.     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

Low-reflectivity in-line variable attenuator utilizing opticalfiber tapers

A single-mode inline variable optical attenuator utilizing optical fiber tapers is discussed. Optical attenuation control is achieved through axial separation between two tapers with beveled endfaces aligned within a ceramic sleeve. Increased axial separation causes increased coupling loss between the two taper fundamental modes. Insertion loss of <0.5 dB, attenuation of >75 dB with continuous 0.05 dB resolution, and reflection return loss of better than 58 dB have been realized. Theoretical studies indicate low polarization and wavelength dependence, and inherent insertion loss of <0.1 dB. This design also exhibits simplicity of fabrication     

一种5~6 GHz宽带全集成CMOS低噪声放大器

采用55 nm标准CMOS工艺,设计并流片实现了一种应用于Wi-Fi 6(5 GHz)频段的宽带全集成CMOS低噪声放大器(LNA)芯片,包括源极退化共源共栅放大器、负载Balun及增益切换单元。在该设计中,所有电感均为片上实现;采用Balun负载,实现信号的单端转差分输出;具备高低增益模式,以满足输入信号动态范围要求。测试结果表明,在高增益模式下该放大器的最大电压增益为20.2 dB,最小噪声系数为2.2 dB;在低增益模式下该放大器的最大电压增益为15 dB,最大输入1 dB压缩点为-3.2 dBm。芯片核心面积为0.28 mm²,静态功耗为10.2 mW。     

Erbium-doped fiber amplifier with 54 dB gain and 3.1 dB noisefigures

It is shown that for practical pump powers (<100 mW) a combination of high gain (>33 dB) and low noise figure (3 dB) cannot simultaneously be achieved with a conventional codirectionally pumped EDFA. However, using a codirectionally pumped composite EDFA incorporating an isolator overcomes the problem, and an amplifier with 51 dB (54 dB) gain and 3.1 dB noise figure (NF) for only 45 mW (93 mW) of pump power is demonstrated