New high accuracy CMOS current conveyors

In this paper, a new CMOS CCII⁺ is proposed. The circuit is characterized by high precision in voltage tracking and exhibits very low input resistance. An adaptive voltage offset cancellation methodology is introduced and then applied to the proposed circuit. As a result, a higher accuracy CCII⁺ is presented. For both circuits, the voltage offset cancellation is independent of the input current and voltage. To demonstrate the strength of the proposed architectures, fair comparisons with Liu and Yodprasit CCII realizations are held.     

新型差动输入CMOS电流传送器及其应用

基于P阱CMOS工艺提出了一种新的差动输入电流传送器。通过引入误差抑制负反馈电路,有效地减小了信号失真,拓宽了电路线性动态范围。文中还详细分析了电路性能,并由此指导电路的优化。给出的几个典型应用电路表明,与第二代电流传送器（CCII）相比,差动输入电流传送器的通用性更强,可获得较简洁的电路结构。本文最后设计了一个既可作为电流模式又可作为电压模式的MOSFET－C二阶滤波器。PSPICE模拟表明所提出的电路与其它同类电路相比具有更好的电路特性。     

CMOS highly linear fully differential current conveyor

Design of a CMOS robust low-distortion fully differential second-generation current conveyor (CCII) is presented. The proposed circuit is essential to extend the use of the CCII-based circuits to high-performance VLSI applications. The design avoids using current mirror(s) in the signal path in order to minimise the distortion caused by mismatched mirroring transistors. The proposed circuit is implemented in a standard 0.5 /spl mu/m CMOS technology and its different characteristics are measured. Statistical measurement results show that the proposed fully differential CCII exhibits total harmonic distortion (THD) of -78.9 dB associated with less than 0.1 dB variation.     

A single current conveyor-based low voltage low power bootstrap circuit for ElectroCardioGraphy and ElectroEncephaloGraphy acquisition systems

In this letter we propose a novel low voltage and low power single-CCII bootstrap circuit specifically designed to be implemented as input stage in ElectroCardioGraphy (ECG) or ElectroEncephaloGraphy (EEG) acquisition systems. The proposed circuit implements only a second generation current conveyor that has been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. Moreover, simulation results are also presented for a two electrodes ECG system. The circuit, designed in a standard 0.35 μm CMOS technology, shows low voltage (1.5 V) low power (28 μW) characteristics, so it is particularly suitable for portable applications.     

Two digitally programmable gain amplifiers based on current conveyors

Two digitally programmable gain amplifiers based on current conveyors (CCIIs) are presented. The first digitally programmable gain amplifier consists of a CCII, an operational transconductance amplifier (OTA), and current mirrors. The second one is composed of current conveyor analogue switches (CCASs). Both proposed digitally programmable gain amplifiers do not need switches but they maintain the linear gain at any digital signal levels similar to the digitally programmable gain amplifier using switches; hence the proposed amplifiers are easier to realize, use narrower chip area, and consume lower power. The first proposed amplifier is verified by constructing the circuit using the CCII in an AD844 IC, the OTA in a CA3080 IC, and some bipolar current mirrors. The second proposed amplifier is verified by simulating the circuit using the parameters extracted from the layout (including parasitic capacitance) in the 0.25 μm MOS technology, the level 49 MOS model obtained through MOSIS is used. The results show that the operations of two proposed amplifiers are in accordance with the theories.     

A differential-input,differential-output current mode operational amplifier

A current operational amplifier with differential input and differential output is described. The amplifier is based on the parallel connection of a CCII+ current conveyor and a CCII? current conveyor followed by a differential output transconductance gain stage. The performance of the amplifier is analysed and experimental results obtained from an implementation using standard operational amplifiers and current mirrors realized using transistor arrays are presented and compared to the theoretical analysis. It is concluded that the static small signal open loop gain and the frequency response matches the performance of conventional voltage operational amplifiers. The input offset and bias errors and the common mode rejection are shown to be strongly dependent on the matching accuracy of the current mirrors used in the conveyors. The proposed configuration can easily be integrated into a monolithic amplifier in either CMOS or bipolar technology.     

一个0.9V低电压双端输出第二代电流传输器的设计

介绍一个0.9 V低电压双端输出第二代电流传输器(DOCCⅡ)的设计。输入级采用衬底驱动MOSFET有效地避免了阈值电压的限制;同时采用了局部正反馈技术提高了带宽增益,因此DOCCII获得了更好的电压跟随特性。该设计电路在标准0.18μm CMOS工艺下,采用Cadence Spectre和BSIM3v3模型对其进行了调试和仿真。仿真结果显示该DOCCII具有4.8MHz的带宽,同时具有比较高的线性度和很好的输入输出电阻。     

A wide dynamic range continuously adjustable CMOS current mirror

A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current     

High input impedance voltage-mode universal biquadratic filter using two OTAs and one CCII

A three-input and single-output voltage-mode universal biquadratic filter with high input impedance, using only two operational transconductance amplifiers (OTAs), one plus-type second-generation current conveyor (CCII) and two capacitors, is presented. The proposed circuit can realize all the standard filter responses, that is, highpass, bandpass, lowpass, notch and allpass filters, from the same configuration. The proposed circuit has no requirements for component matching conditions.     

Low-voltage high-drive CMOS current feedback op-amp

A novel CMOS current feedback op-amp is presented. The solution works using a low supply voltage and provides a wide input/output swing as well as a high current driving capability. Experimental results from a prototype implemented in a 0.35-/spl mu/m technology and powered with 1.5 V are also given. The circuit exhibits a better than 500 kHz closed-loop bandwidth and a /spl plusmn/1 mA current drive capability.     

Design of second-generation current conveyors employing bacterial foraging optimization

The present paper deals with the optimal sizing of CMOS positive second-generation current conveyors (CCII+) employing an optimization algorithm. A contemporary non-gradient stochastic optimization algorithm, called bacterial foraging optimization (BFO) algorithm, has been employed to obtain the optimal physical dimensions of the constituent PMOS and NMOS transistors of the CCII+. The optimization problem has been cast as a bi-objective minimization problem, where we attempt to simultaneously minimize the parasitic X-port input resistance (R_X) and maximize the high end cut-off frequency of the current signal (f_ci). The results have been presented for a large selection of bias currents (I₀) and our proposed algorithm could largely outperform a similar algorithm, recently proposed, employing particle swarm optimization (PSO) algorithm and also the differential evolution (DE) algorithm.     

Universal filter using plus-type CCIIs

A universal second-order filter circuit with voltage gain using only plus-type current conveyors (CCIIs) is presented. The circuit offers several advantages, such as high input impedance, low filter sensitivities to passive elements, use of grounded capacitors and independent control of ω₀, Q and voltage gain with separate grounded resistors. The use of only one type (plus-type or minus-type) of CCII simplifies the configuration     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

一种集成低压低功耗电流复制电路设计

本文提出了一种集成低压低功耗电流复制电路。利用单级放大器和电压跟随器构成的负反馈回路实现对输入电压跟的跟随,利用等比例电阻实现电流的等比例复制,电路结构简单,仅由5个MOS管和2个等比例电阻构成。基于TSMC 0.18μm工艺完成电路设计,使Spectre完成电路仿真。结果表明,电路电源电压为1V时,电路静态功耗仅为1μW。在输入电流范围为0-50μA时,输出电流线性跟随输入电流,当输入电流大于3μA时,电流复制精度大于99%,电路带宽为31MHz。     

Wideband CMOS current conveyor

A novel CMOS second generation current conveyor (CCII) for high frequency current-mode signal processing is described. The input stage consists of a regulated current cell coupled to a source follower, and the output stage is a cascode current mirror. This architecture provides the high input/output conductance ratio for current transfer. Simulations show that a 3 dB bandwidth extends beyond 100 MHz     

A multi-port D-R mutator using CCIIs with current followers

A multi-port D-R mutator with new current conveyors (CFCCIIs) as the four-port active element is proposed. Each CFCCII consists of a current follower added to a second-generation current conveyor (CCII). This proposed circuit is a simple configuration using CCIIs, CFCCIIs and grounded capacitances and is applied to higher order high-pass filters. This configuration can realize a superior transmission characteristic, inheriting the characteristic of the conventional LC filter. Since all the passive elements are grounded, the influence of parasitic elements of current conveyors can be reduced with this circuit configuration. As a result, this circuit is considered a suitable configuration for monolithic integration. Results obtained from the SPICE simulations show the realized filters have excellent performance and the circuit is effective.     

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.     

Universal active current filters using single second-generation current conveyor

Two novel universal active current filters with a single second-generation current conveyor (CCII), which use fewer passive RC elements and have a larger quality factor than the previous two filters proposed by the author, are presented.<>     

On the use of current sensors for the control of power converters

This paper describes the use of current sensors for the control of power converters. No voltage sensor is required in the whole system. The sensed current and the rate of change of the inductor current in different circuit topologies are used to determine the input and output voltages of the converters, and for current programming and maximum current protection. Apart from reducing the number of sensors, the proposed method provides inherent electrical isolation between the power conversion stage and the controller and lessens noise-coupling problems. The proposed technique is illustrated with a current-programmed DC/DC boost regulator with feedforward and feedback control. The regulator's steady state and transient responses under input source and output load disturbances are presented.     

A high-speed current conveyor based current comparator

In this paper, a new high-speed current mode comparator based on inherent current conveyor and positive feedback properties is presented. This novel approach has resulted in major reduction of the response time and hence a wide band application of the circuit. Simulation results using HSPICE and 0.18 μm CMOS technology with 1.8 V supply confirms a propagation delay of less than 0.4 ns in the high frequency range of 700 MHz with 158 μw power dissipation. Under the above conditions, the accuracy of the input current is as low as 50 nA.