Role of ultrathin Al2O3 layer in organic/inorganic hybrid gate dielectrics for flexibility improvement of InGaZnO thin film transistors

We investigated flexible amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) on a polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and ultrathin Al₂O₃. IGZO TFTs were fabricated with hybrid PVP/Al₂O₃ gate dielectrics having Al₂O₃ layers of different nanoscale thicknesses, which were deposited by atomic layer deposition (ALD). The electrical characteristics of the TFTs with the organic/inorganic hybrid gate dielectrics were measured after cyclic bending up to 1,00,000 cycles at the bending radius of 10 mm. The ultrathin Al₂O₃ layer in the hybrid gate dielectrics improved the mechanical flexibility and protected the organic gate dielectric against damage during the sputter deposition of the IGZO layer. Finite elements method (FEM) simulations along with the structural characterization of the cyclically bent device showed the importance of optimizing the thickness of the Al₂O₃ layer in the hybrid gate dielectrics to obtain mechanically stable and flexible a-IGZO TFTs.     

Organic Electronics: High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment (Adv. Funct. Mater. 16/2010)

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

La2O3 gate dielectrics for AlGaN/GaN HEMT

The annealing temperature dependent electrical characteristics of La₂O₃ gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (V_th) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La₂O₃ and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La₂O₃ film, which is useful to limit the reduction in gate capacitance. A high k-value for La₂O₃ gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.     

Ultra-thin polymer gate dielectrics for top-gate polymer field-effect transistors

We have demonstrated top-gate polymer field-effect transistors (FETs) with ultra-thin (30–50 nm), room-temperature crosslinkable polymer gate dielectrics based on blending an insulating base polymer such as poly(methyl methacrylate) with an organosilane crosslinking agent, 1,6-bis(trichlorosilyl)hexane. The top-gate polymer transistors with thin gate dielectrics were operated at gate voltages less than ?8 V with a relatively high dielectric breakdown strength (>3 MV/cm) and a low leakage current (10–100 nA/mm² at 2 MV/cm). The yield of thin gate dielectrics in top-gate polymer FETs is correlated with the roughness of underlying semiconducting polymer film. High mobilities of 0.1–0.2 cm²/V s and on and off state current ratios of 10⁴ were achieved with the high performance semiconducting polymer, poly(2,5-bis(3-alkylthiophen-2yl)thieno[3,2-b]thiophene.     

Improved pentacene device characteristics with sol–gel SiO2 dielectric films

The interfacial interactions between semiconductors and gate dielectrics have a profound influence on the device characteristics of field effect transistors (FETs). This paper reports on the concept of introducing a sol–gel SiO₂ as inorganic capping layer to significantly improve device characteristics of pentacene-based FETs. The smoother film surfaces of sol–gel SiO₂ (1.9 Å root-mean-square) induced larger pentacene grain sizes, and led to hole mobilities of 1.43 cm²/Vs, on–off ratio of 10⁷, and a subthreshold swing of 102 mV/decade when operating at −20 V.     

High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

Air stable C60 based n-type organic field effect transistor using a perfluoropolymer insulator

Air stable n-type organic field effect transistors (OFETs) based on C₆₀ are realized using a perfluoropolymer as the gate dielectric layer. The devices showed the field-effect mobility of 0.049 cm²/V s in ambient air. Replacing the gate dielectric material by SiO₂ resulted in no transistor action in ambient air. Perfluorinated gate dielectric layer reduces interface traps significantly for the n-type semiconductor even in air.     

Modeling and Understanding the Compact Performance of h-BN Dual-Gated ReS2 Transistor

In this study, high-performance few-layered ReS₂ field-effect transistors (FETs), fabricated with hexagonal boron nitride (h-BN) as top/bottom dual gate dielectrics, are presented. The performance of h-BN dual gated ReS₂ FET having a trade-off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h-BN dielectric has almost no defects and provides a physical distance between the traps in the SiO₂ and the carriers in the ReS₂ channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h-BN dual-gated ReS₂ with a high mobility of 46.1 cm² V⁻¹ s⁻¹, a high current on/off ratio of ≈10⁶, a subthreshold swing of 2.7 V dec⁻¹, and a low effective interface trap density (N_t,eff) of 7.85 × 10¹⁰ cm⁻² eV⁻¹ at a small operating voltage (<3 V). These phenomena are demonstrated through not only a fundamental current–voltage analysis, but also technology computer aided design simulations, time-dependent current, and low-frequency noise analysis. In addition, a simple method is introduced to extract the interlayer resistance of ReS₂ channel through Y-function method as a function of constant top gate bias.     

High permittivity dielectrics for poly(3-alkylthiophene) field-effect transistor devices

In an attempt to disentangle the effects of permittivity and surface energy of the gate insulator (expressed by its dielectric constant k and water contact angle, respectively) on the performance of organic field-effect transistors (FETs), we fabricated top- and bottom-gate FET architectures with poly(3-alkylthiophenes) (P3ATs) of different side-chain lengths, using a range of gate dielectrics. We find that this class of semiconductor, including the short butyl-(C₄-) substituted derivative, is significantly less susceptible to the often detrimental effects that high-k dielectrics can have on the performance of many organic FETs. For bottom gate devices we identify the surface energy of the gate dielectric to predominantly dictate the device mobility.     

ZrO2 insulator modified by a thin Al2O3 film to enhance the performance of InGaZnO thin-film transistor

A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO₂–Al₂O₃ bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO₂ single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of I_on/I_off ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm²/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 10¹² to 2.5 × 10¹² cm⁻². The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al₂O₃ films to modify the high-k ZrO₂ dielectric.     

ZnO TFT Devices Built on Glass Substrates

ZnO thin-film transistors (TFTs) were built on glass substrates. The device with a top gate configuration operates in the depletion mode. The ZnO channel was grown by metalorganic chemical vapor deposition (MOCVD) on glass at low temperature. SiO₂ was used as the gate dielectric. The TFT has an on/off ratio of ∼4.0 × 10⁴ and a channel field-effect mobility of ∼4.0 cm²/V s. The average transmittance of the ZnO film in the visible wavelength is ∼80%. To compare the characteristics of the TFTs prepared by using a poly-ZnO and epitaxial-ZnO channel, an epi-ZnO TFT with the same configuration and dimensions was made on an r-Al₂O₃ substrate. The epi-ZnO TFT shows higher field-effect mobility of ∼35 cm²/V s and on/off ratio of ∼10⁸.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.     

Experimental study for high effective mobility with directly deposited HfO2/La2O3 MOSFET

We experimentally examine the effective mobility in nMOSFETs with La₂O₃ gate dielectrics without SiO_x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N_s = 5 × 10¹¹ cm^?2 in the low 10¹¹ cm^?2 eV^?1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.     

Device characteristics of perylene-based transistors and inverters prepared with hydroxyl-free polymer-modified gate dielectrics and thermal post-treatment

Organic field-effect transistors (OFETs) and complementary inverters were produced on the basis of n-type N,N′-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C8) using the neutral cluster beam deposition (NCBD) method. Significant improvements in surface morphology and crystallinity were observed after the surface modification of SiO₂ gate dielectric layers with hydroxyl-free polymer insulators such as polymethylmethacrylate (PMMA) and cyclic olefin copolymer (COC), and thermal post-treatment. Electric characteristics and operational stability of PTCDI-C8-based OFETs were also clearly enhanced after the surface modification, and in particular, the thermally post-treated OFETs with COC-modified SiO₂ gate dielectrics exhibited a high room-temperature mobility of 0.68 cm²/V s. Two structural types (generic vs. encapsulated) of inverters in top-contact configuration were fabricated by integration of the p-type pentacene and n-type PTCDI-C8 OFETs using COC-modified SiO₂ gate dielectrics. Due to the increased electron mobilities and good coupling between p- and n-type OFETs, hysteresis-free, fast-switching inverters were realized with high gains of ∼20 in the first and third quadrants of voltage transfer characteristics under ambient conditions. The device characteristics of the encapsulated inverters monitored as a function of the time were well maintained with slight degradation.     

Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness down to 1.9 nm are discussed.     

Solution-processed natural gelatin was used as a gate dielectric for the fabrication of oxide field-effect transistors

Biocompatible and biodegradable materials are attractive for environmentally safe, flexible and biosustainable devices since they are nontoxic renewable materials with a low cost. Gelatin, a natural protein, is a promising biopolymer for photography, cosmetic manufacturing and food. In this paper, solution-processed natural gelatin was used as a gate dielectric for the fabrication of oxide field-effect transistors (FETs). Similarly to a polyelectrolyte, mobile ions can be generated in gelatin in air environment. A high gate specific capacitance larger than 0.93 μF/cm² was obtained in gelatin processed at low concentrations, due to the formation of electric-double-layers (EDLs). As gelatin films processed at a low concentration of 0.02 g/mL, the fabricated FETs showed excellent electrical performances. The average current on/off ratio and the mobility were estimated to be 1.36 × 10⁵ and 33.2 cm²/V, respectively. The proposed technique may be application in the bioelectronics field, including biosensors and synaptic devices.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

Selection of rare earth silicates for highly scaled gate dielectrics

An aggressive equivalent oxide thickness (EOT) scaling with high-k gate dielectrics has been demonstrated by ultra-thin La₂O₃ gate dielectric with a proper selection of rare earth (La-, Ce- and Pr-) silicates as an interfacial layer. Among silicates, Ce-silicate has shown the lowest interface-state density as low as 10¹¹ cmv⁻²/eV with a high dielectric constant over 20. n-Type field-effect transistor (FET) with a small EOT of 0.51 nm has been successfully fabricated with a La₂O₃ gate dielectric on a Ce-silicate interfacial layer after annealing at 500 °C. Negative shift in threshold voltage and reduced effective electron mobility has indicated the presence of fixed charges in the dielectric. Nonetheless, the high dielectric constant and nice interfacial property of Ce-silicate can be advantageous for the interfacial layer in highly scaled gate dielectrics.