基于CMOS工艺的低噪声、高增益混频器

基于TSMC 0.18μm CMOS工艺,设计了一种低噪声、高增益的混频器.通过在吉尔伯特单元中的跨导级处引入噪声抵消技术以降低混频器的噪声;并且在开关管的源级增加电流注入电路的基础上并联一个电容与开关管共源节点处的寄生电容谐振,进一步降低混频器的噪声,增大电路的增益.仿真结果表明,在本振（LO）频率为2.395 GHz,射频（RF）频率为2.4GHz时,混频器的增益为14.2dB,双边带噪声系数为5.9dB,输入三阶交调点为-3.2dBm.混频器工作电压1.8V,直流电流为8mA.     

5.8 GHz CMOS混频器设计

介绍了CMOS混频器主要技术指标的设计思路和技术.采用O.18 μm CMOS工艺,使用Agilent公司的ADS软件设计出一种5.8 GHz CMOS混频器电路,结果表明,工作电压1.8 V时,RF频率5.8 GHz,本振频率5.78 GHz,中频频率20 MHz下,转换增益7.3 dB、输入1 dB压缩点-8.3 dBm,噪声系数8.7,工作电流小于5 mA,该电路已交付流片.     

四类LO信号对CMOS Gilbert混频器增益影响分析

本文深入研究了CMOS Gilbert混频器在四类本振信号(Local Oscillator,LO)作用下的开关模型,提出了相应情况下的混频器电压转换增益修正公式。基于0.25μm标准CMOS工艺的Gilbert混频器仿真结果表明,本文预测的电压增益理论值与仿真结果相差最大为0.08dB,对CMOS混频器的优化设计具有指导意义。     

An analysis of high-frequency noise in RF active CMOS mixers

An analysis of high-frequency noise in RF active CMOS mixers including single-balanced and double-balanced architectures is presented. The analysis investigates the contribution of non-white gate-induced noise to the output noise power as well as the spot noise figure (NF) of the RF CMOS mixer. It accounts for the non-zero correlation between the gate-induced noise and the channel’s thermal noise. The noise contribution of the RF transconductor and the switching pair to the output noise power is studied. Experimental results verify the accuracy of the analytical model. Payam Heydari (S’98–M’00) received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, where he worked on noise analysis in deep submicrometer very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, RF, and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Mention Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who’s Who in America. Dr. Heydari Professor Heydari has been the Associate Editor of IEEE TRANS. ON CIRCUITS AND SYSTEMS, I, since 2006. He currently serves on the Technical Program Committees of International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003.     

5.8GHz WLAN CMOS双平衡混频器的设计

介绍了基于0．18μm CMOS工艺的802．11a无线局域网（WLAN）有源双平衡混频器的设计方法。该混频器射频（RF），本振（LO）和中频（IF）信号频率分别为5．8GHz，4.6GHz和1．2GHz。仿真结果显示：在1．8V电压下；变频增益为4．27dB，单边带噪声系数为10．73dB，1dB压缩点为-13．18dB，三阶输入截点为-3．04dB，功耗为32．4mW，芯片面积为1．8mm×1mm。     

一种具有新型增益控制技术的CMOS宽带可变增益LNA

高速超宽带无线通信的多标准融合是未来射频器件的发展趋势,该文提出一种基于CMOS工艺、具有新型增益控制技术的宽带低噪声放大器(LNA),采用并联电阻反馈实现宽带输入匹配,并引入噪声消除技术来减小噪声以提高低噪声性能;输出带有新型6位数字可编程增益控制电路以实现可变增益。采用中芯国际0.13m RF CMOS工艺流片,芯片面积为0.76 mm2。测试结果表明LNA工作频段为1.1-1.8 GHz,最大增益为21.8 dB、最小增益8.2 dB,共7种增益模式。最小噪声系数为2.7 dB,典型的IIP3为-7 dBm。     

CMOS混频器设计现状与进展

详细阐述了CMOS混频器设计技术的进展，着重介绍了CMOS混频器各项性能优化技术的现状与进展，探讨了各种技术的优缺点。最后，总结了CMOS混频器有关转换增益、线性度以及噪声系数的成果报道。     

A low-noise mixer with an image-reject notch filter for 2.4 GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4 GHz industrial-scientific-medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0 dB improvement of single-side band noise figure, about 2.9 dB power conversion gain improvement, and 25 dB image suppression compared to those without the filter dissipating 4 mA from a 2.5 V supply voltage.     

基于微带线的W波段二次分谐波混频器设计

采用微带混合集成电路技术设计了一款W波段二次分谐波混频器.通过分析二级管封装结构引入的寄生参量,提出了一种减小二级管并联寄生电容的方法.为了避免在W波段使用传统分谐波混频器中普遍使用的过孔接地及侧边平行耦合微带线带通滤波器,提出了一种改进型分谐波混频器结构.测试结果表明混频器在本振频率为45 GHz,中频频率为2.4 GHz时单边带变频损耗最小,最小值为8 dB.射频频率在90 ～ 100 GHz测试频率范围内,变频损耗的测量值小于10.5 dB.     

CMOS 射频低噪声放大器的设计

讨论了CMOS射频低噪声放大器的相关设计问题,对影响其增益、噪声系数、线性度等性能指标的因素进行了分析,并综述了几种提高其综合性能指标的方法。在此基础上,采用SMIC0．25μm CMOS工艺库,给出了3．8GHz CMOSLNA的设计方案。HSPICE仿真结果表明：电路的功率增益为13．48dB,输入、输出匹配良好,噪声系数为2．9dB,功耗为46．41mw。     

一种高线性度CMOS混频器的设计

采用线性化技术改进的混频器结构提高了线性度.采用TSMC 0.18 μm RF CMOS模型进行了电路仿真.仿真结果:在电源电压为1.8 V时,输入三阶截断点(IIP3)为10.3 dBm,输入1dB压缩点(P-1dB)为-3.5 dBm,增益为9.2 dB,单边带噪声系数为17 dB.     

一种高线性的UWB接收机下变频混频器设计

该文介绍了一种UWB下变频混频器的设计思路和技术。在TSMC0.18μmCMOS工艺下,使用Agilent公司的ADS软件设计出一种3~5GHz的CMOS混频器电路。仿真结果表明,工作电压3V时,RF频率为3.169GHz,本振频率为3.434GHz,中频频率为265MHz,转换增益为15.4dB,双边带噪声系数低于13.3dB,P1dB压缩点为-13dBm,工作电流为4.6mA。     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

一种改进的高线性CMOS混频器的分析与设计

在多标准系统应用中,由于线性度和噪声的要求,使得混频器的设计难度很大。采用2次谐波注入结构的3阶失真抵消技术,设计了一种改善跨导级线性度的高线性CMOS混频器。在混频器开关级处引入LC滤波电路,抵消了开关级晶体管的2阶和3阶互调失真,进而优化了开关级的线性度。采用TSMC 0.13 μm CMOS工艺进行设计与仿真,并完成了版图设计与流片。较之传统的吉尔伯特混频器,该电路的输入3阶交调点IIP3增加了11.2 dBm,达到9.2 dBm的高线性度,对噪声系数、增益以及功耗造成的影响较小。     

具有高可调增益范围的CMOS宽带中频调制器

利用TSMC 0 .2 5 μmCMOS混合工艺 ,针对超外差结构的无线宽带收发器 ,实现了一个能够工作在 5 0～6 0 0MHz的中频调制器 ,并对该调制器进行了仿真和测试。由于该调制器在输出端采用了一个具有高可调增益范围而且鲁棒性能好的可变增益放大器 (VGA) ,从而使得该调制器具有超过 70dB的增益可调范围。测试结果表明 ,该调制器能够工作在 5 0～ 6 0 0MHz的频率上 ,输出功率为 - 81～ - 10dBm ,最小增益的输出噪声为 - 130dBm/ Hz,最大增益的输出P1dB点为 - 4 .3dBm ,在 3V的电源电压下 ,电流功耗为 32mA。     

CMOS全差分超宽带低噪声放大器

文中给出了一个应用于超宽带射频接收机中的全集成低噪声放大器,该低噪声放大器采用了电阻并联负反馈与源极退化电感技术的结合,为全差分结构,在Jazz0.18μm RF CMOS工艺下实现,芯片面积为1.08mm2,射频端ESD抗击穿电压为1.4kV。测试结果表明,在1.8V电源电压下,该LNA的工作频带为3.1～4.7GHz,功耗为14.9mW,噪声系数(NF)为1.91～3.24dB,输入三阶交调量(IIP3)为-8dBm。     

CMOS 混频器的设计技术

无线技术的发展对收发信机前端电路提出的新要求是：高的工作频率,低电压,低功耗,高度集成。混频器是射频前端电路中进行频率变换的十分重要的模块,主要介绍了CMOS混频器的基本工作原理,实现混频的一些常见结构。这些结构的优缺点。并介绍了当前CMOS混频器的主要电路设计技术以及作者在混频器跨导线性度分析方面进行的研究,文中还给出了作者设计的一个新型混频器的结构。     

一种应用于6-9GHz UWB系统的低噪声CMOS射频前端设计

本文介绍了一种应用于6-9 GHz超宽带系统的全集成差分CMOS射频前端电路设计。在该前端电路中应用了一种电阻负反馈形式的低噪声放大器和IQ两路合并结构的增益可变的折叠式正交混频器。芯片通过TSMC 0.13µm RF CMOS工艺流片,含ESD保护电路。经测试得该前端电路大电压增益为23~26dB,小电压增益为16~19dB;大增益下前端电路平均噪声系数为3.3-4.6dB,小增益下的带内输入三阶交调量(IIP3)为-12.6dBm。在1.2V电压下,消耗的总电流约为17mA。     

DESIGN AND IMPLEMENTATION OF CMOS IMAGE SENSOR

I. Introduction Complementary Metal Oxide Semiconductor (CMOS) image sensor has been becoming in-creasingly significant in the field of solid image sensor. Compared with Charge-Coupled Device (CCD) image sensor, CMOS image sensor possesses many advantages, such as smaller size, more con-venient to be integrated with other devices, lower power consumption and cost, etc[1,2]. To date, CMOS image sensor is adopted in almost all mo-biles which can take pictures. In addition, CMOS image …     

一种具有温度补偿的宽带CMOS可变增益放大器

设计实现了一个具有温度补偿的宽带CMOS可变增益放大器,该可变增益放大器的核心电路由三级基于改进型Cherry-Hooper结构的可变增益单元级联而成,并通过一种温度系数增强的且可编程的偏置电路和增益控制电路对可变增益放大器的增益进行温度补偿。采用中芯国际0.13μm CMOS工艺流片,测试结果表明可变增益放大器的可变增益范围为-13～27dB,经过温度补偿后,在相同增益控制电压下其增益在0～75°C温度范围内的变化范围不超过3dB。可变增益放大器的3dB带宽为0.8～3GHz,输入1dB压缩点为-50～-21dBm,在1.2V电压下,功耗为21.6mW。