A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.     

Low-power MicroVrms noise neural spike detector for implantable interface microsystem device

In this paper, an ultra-low-power and low-noise spike detector is proposed for massive integration in the implantable multichannel brain neural recording device. The detector circuit with nonlinear energy operator (NEO) algorithms achieves the spike detecting from action potential including complex noise. The spike detector circuit consists of a differentiator with a fully-differential structure and a multiplier based on CMOS translinear using sub-threshold technique. The differentiator has the steepness of a transmission function with frequency +20 dB/dec, frequency response from 10 Hz to 10.5 kHz. The linear range of multiplier is from −0.9 V to 0.9 V at V_DD = ±1.65 V. The spike detector is implemented in 0.35 μm technology with fully-CMOS process. One detector die size is 0.0187 mm² and its total current consumption of 825 nA. As is demonstrated by measured results, the proposed circuit has detected the instantaneous energy of the input real spike signals well, which the noise of small than 218 μV_rms over a nominal bandwidth of 500–10.5 kHz.     

Successive-divider-line ADC dedicated to low-power medical devices

A low-power and small silicon area digitally controlled Switched Mode Power Supply (SMPS) is intended for the minimization of both power and size of an on-chip DC power supply building block which is mainly dedicated for implantable medical sensing and microstimulation devices. Such SMPS is based on a successive divider-line analog-to-digital Converter (SDLADC), which is the focus of this paper. Special attention is paid for reducing the power consumption and silicon area of this SDLADC, which consists of a resistor network based on diode connected transistor used to replace the delay-line of the windowed ADC. To compensate process and temperature variations, a digital calibration technique is used to meet the specified static and dynamic output voltage regulations and avoid variations of the regulated SMPS output voltage. The proposed ADC is implemented in AMS 0.35 μm CMOS process. Simulation results show a current consumption of 1.5 μA/MHz and conversion time of 10 ns much lower than recent conventional topology values. The proposed circuit exhibits a quantization steps smaller than 1.6% of V_ref and it can be a solution for high switching frequency, which results on faster regulation of SMPS output voltage.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

A novel current-mode four-quadrant CMOS analog multiplier/divider

This paper presents, a new current mode four-quadrant CMOS analog multiplier/divider based on dual translinear loops. Compared with the previous works this circuit has a simpler structure resulting in lower power consumption and higher frequency response. Simulation results, performed using HSPICE with 0.25 μm technology, confirm performance of the proposed circuit.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

Low-voltage low-power FGMOS based VDIBA and its application as universal filter

This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.     

A novel configuration for UWB LNA suitable for low-power and low-voltage applications

Two UWB LNAs based on a new configuration suitable for low-power and low-voltage applications are presented. The proposed configuration saves bias circuit because of sharing only a bias circuit. In designing LNA-1 good phase linearity property achievement is followed for low-power and low-voltage applications, while in LNA-2 the main concerns are high power gain, by keeping low-power consumption, and small chip area. By taking advantages of resistive-feedback and RLC load, wideband input matching is obtained. Based on the proposed configuration, accompany with complete noise analysis, noise of LNA-2 is highly suppressed and flat noise figure is reaped. The 130 nm CMOS LNA-1 and LNA-2 dissipate 2.95 mW and 6.09 mW, respectively, from 0.7 V supply voltage, without using of forward-body-bias technology. Input return loss of both LNAs is below than ?10.5 dB while LNA-1 achieves average power gain of 9 dB and LNA-2 17 dB. The group-delay variation of LNA-1 is about ±6.1 ps over the band of 3.1–10.6 GHz. The NF of LNA-2 is 2.4–2.89 dB over the whole band of interest.     

Low-voltage,low-power Vt independent voltage reference for bio-implants

Biomedical electronics trends focus mainly on portability, miniaturization, connectivity, humanization, security and reliability. In this scenario, digital, low-cost CMOS technology plays a key role, especially in implementing complex systems into small devices with no batteries that can even be implanted in humans. Due to patient safety, the implanted devices are faced with challenges: device operation temperature and the RF power link must be kept extremely low.By using proper topologies, the whole system can be designed to operate in low-voltage and low-power modes to maintain low temperature and avoid tissue thermal hazards. In this paper, a voltage reference is proposed which can operate at as low as 500 mV with power consumption less than 100 nW. Furthermore, the proposed topology, based on composite transistors operating in weak inversion, shows a good rejection to threshold voltage V_t, which is an inherent CMOS dispersion parameter. Simulation results using the process corners show that the V_t dependence can be reduced to less than ±2% (3σ) at the body temperature and the PSRR can be as large as 65 dB for higher frequencies. One of the key features of the circuit is its simple design.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.     

Miniaturized microstrip bandpass filter designed using rectangular dual spiral resonator

A miniaturized microstrip bandpass filter based on a rectangular dual spiral resonator (DSR) is proposed in this paper. The rectangular DSR bandpass filter is centered at 3.65 GHz to suit for Wireless LAN (IEEE802.11y) application. The proposed filter offers transmission zero at the high side of out-of-band response. Across the bandwidth, the measured minimum insertion loss is about 1.7 dB, while the measured return loss is better than 19 dB. Measurement results are good agreement and closed to the simulated ones. The total circuit size of the miniaturized bandpass filter is about 0.145λ_g by 0.135λ_g, where λ_g is the guided wavelength at 3.65 GHz.     

Electrical properties of Π-conjugated Fe-TPP molecular solar cell device

A heterojunction device of Au/Fe-TPP/n-Si/Al was assembled by thermally evaporated deposition. The dark current density–voltage characteristics of device were investigated. Results showed a rectification behavior. Measurements of thermo electric power confirm that Fe-TPP thin film behaves as p-type semiconductors. Electronic parameters such as barrier height, diode ideality factor, series resistance, shunt resistance were found to be 0.83 eV, 1.5, 7 × 10⁵ Ω and 2 × 10¹⁰ Ω, respectively. The Au/Fe-TPP/n-Si/Al device indicates a photovoltaic behavior with an open circuit voltage V_oc of 0.52 V, short circuit current I_sc of 2.22 × 10^?6 A, fill factor FF of 0.49 and conversion efficiency 1.13% under white light illumination power 50 W/m².     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Post-fabrication electric field and thermal treatment of polymer light emitting diodes and their photovoltaic properties

This work presents post-fabrication electric field and heat treatment methods developed for polymer light emitting diodes (PLEDs), which have degraded due to exposure to oxygen and water vapors during low-cost fabrication performed in standard room conditions. Investigated PLEDs have structures composed of indium tin oxide (ITO), poly(3,4-ethylenedioxythiophene), poly(styrenesulfonate), (PEDOT:PSS), poly[2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), and aluminum (Al). Heat treatment restores the light emitting function of dysfunctional PLEDs but also causes a high turn-on voltage of 10 V. Electric field treatment utilizing ?1 V reduces this high turn-on voltage to 3 V. This procedure also improves open circuit voltages from 5 mV to 55 mV, and short circuit currents from 0.5 nA to 5 nA when PLEDs are operated as photovoltaic cells under a light intensity of 500 mW/m². Repeated I–V sweep measurements additionally show improved stability and uniformity. The reasons for these improvements, the usage of an optimal treatment temperature of 130 °C, and the usage of treatment voltages of 0 and ?1 V are discussed.     

A low-power low-offset dynamic comparator for analog to digital converters

A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive Monte-Carlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180 nm and 90 nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators.