Transimpedance amplifier with a compression stage for wide dynamic range optical applications

A high dynamic input transimpedance amplifier was implemented in 130 nm CMOS technology. The proposed TIA is an inverter with a diode connected NMOS and a gate controlled PMOS loads which is cascode connected with the inverter. The square law compression NMOS increases the input photocurrent up to 10 mA. The TIA has an integrated input referred noise current of 135 nA, 227 MHz bandwidth. The TIA shows a transimpedance gain of 59 dBΩ and a 97 dB dynamic range. The TIA consumes 2.3 mA from 1.5 V voltage supply.     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

A high performance differential input CMOS current buffer

In this paper, a high accuracy CMOS differential input current buffer (CB) is proposed which employs super source followers (SSF) as input stage and regulated cascode (RGC) current mirrors as output stage. High accuracy requires very high output resistance and low input resistance. Small signal analysis is performed and it is shown that the proposed CB circuit has very low input impedances at ports n and p due to SSF transistors and also very high output impedance at output port due to RGC current mirrors. The simulation results show 9.72 Ω input resistances at ports n and p, 454 MΩ output resistance at output port with only 625 μW power consumption under ±0.9 V power supplies. The simulations are performed with HSpice using TSMC 0.18 μm process parameters and it is shown that the simulation results are in very good agreement with the theoretical ones.     

High rectifier output voltages with printed organic charge pump circuit

It is known that in many wireless organic electronic applications the required supply voltage is higher than the accessible signal amplitude. Therefore, voltage multiplier circuits are needed in many cases. We report a gravure printed organic charge pump circuit operating at 13.56 MHz suitable for rectified voltage amplification in printed electronic devices. The circuit, consisting of four diodes and four capacitors, has been monolithically printed using only high volume production compatible manufacturing methods. With 10 V AC input the output of the circuit at 13.56 MHz is 8.4 V and 11.8 V using 1 MΩ and 10 MΩ output loads, respectively. At 13.56 MHz the output voltage of the charge pump is three times higher than the output of a half-wave rectifier. The results demonstrate the possibility to print efficient high frequency (HF) charge pump circuits to meet the supply voltage requirements of the printed electronic applications.     

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.     

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

A cascade energy band structure enhances the carrier energy in organic vertical-type triodes

Organic vertical-type triodes (OVTs) based on the cascade energy band structure as emitter layer are studied. The electric characteristics were dramatically enhanced while incorporating the cascade energy under current driving and voltage driving modes. The improvement is attributed to that injection carriers can obtain higher energy through a stepwise energy level. When the device has a layered structure of F₁₆CuPC (10 nm)/PTCDI (10 nm)/pentacene (100 nm) in emitter, it exhibits a common-base transport factor of 0.99 and a common-emitter current gain of 225 under current driving mode and exhibits a high current modulation-exceeding ?520 μA for a low collector voltage of ?5 V and a base voltage of ?5 V and the current on/off ratio of 10³ under voltage driving mode. Furthermore, we realized first organic current mirror that exhibited out/in current ratio of 0.75 and output resistance of 10⁵ Ω by using the OVTs.     

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500 μA with offset of 2.2 nA, input resistance of 235 Ω, output resistance of 117 kΩ, current transfer ratio of 0.98, dissipates 0.83 mW power and exhibits bandwidth of 656 MHz which increases to 1.52 GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13 μm technology with a supply voltage of ±0.5 V.     

Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector

This paper presents an Automatic Gain Control (AGC) circuit design with 200–530 μW average power consumption given a 1 V supply. The Variable Gain Amplifier (VGA) therein comes with 0.9 V input range and output stages with a swing of 0.9 V and a minimum bandwidth of 100 MHz. Feed-forward Output Swing Prediction is used to adjust the gain of the VGA corresponding to the signal envelope detected by a Parallel-Detect Singular-Store Peak Detector. At a maximum refresh-rate of 4 MHz, the AGC is capable of adjusting the gain of the VGA within less than 250 ns when the input signal envelope is reduced by 20 dB, and 100 ns when raised by 20 dB. The circuit design is carried out using a 0.18 μm standard CMOS process with a core area of 0.0024 mm².     

A wideband balun–LNA

In this paper a wideband Low Noise Amplifier (LNA) is introduced which also converts the single-ended input to differential signal at the output. It is based on common-source amplifier with active-feedback to provide input matching. The proposed amplifier has the input matched from 500 MHz to 2.5 GHz. It achieves the maximum voltage gain of 24 dB in this band, while the minimum noise figure (NF) is 2.35 dB. The simulated OIP3 of this amplifier is equal to 21 dBm. The LNA has been designed and simulated in a 0.18 μm CMOS process.     

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers

In this paper, a low power Variable Gain Amplifier (VGA) circuit with an approximation to exponential gain characteristic is presented. It is achieved using current mirrors to generate appropriate current signals to bias the input stage of the VGA circuit working in triode region, and the output stage working in saturation region, respectively. The VGA circuit presented herein comes with a 549 μW maximum power consumption given a 1.8 V supply. Most important of all, it has a linear-in-dB 48-dB dynamic gain range per stage. The effect of the input trasconductance and the output resistance on the linearity of gain control is also discussed. This circuit is fabricated using a 0.18 μm standard CMOS process with a core area of 0.0045 mm².     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

Nano-gap micro-electro-mechanical bulk lateral resonators with high quality factors and low motional resistances on thin silicon-on-insulator

The design, fabrication and experimental investigation of 22–25 MHz fragmented-membrane MEM bulk lateral resonators (BLR) with 100 nm air-gaps on thin (1 and 6 μm) silicon-on-insulator (SOI) are reported. Quality factors as high as 120,000 and motional resistances of as little as 60 kΩ are measured under vacuum at room temperature, with 12 V DC bias and low AC power. The temperature influence on the resonance frequency and quality factor is studied and discussed between 80 K and 320 K. Significant quality factor increase and motional resistance reduction are reported at cryogenic temperature. The paper shows that high-quality factor MEM resonators can be integrated on partially depleted thin SOI, which can be a substrate of choice for the fabrication of future integrated hybrid MEMS–CMOS integrated circuits for communication applications.     

A comprehensive,adjustable approach for linearizing and broadening the gain characteristic of variable gain amplifiers

In this paper a comprehensive approach is presented to linearize and adjust gain characteristic of variable gain amplifiers (VGAs). It is also capable of increasing the output linear dynamic range of VGAs and modifying variation range of control voltage. The approach is able to change the voltage gain characteristic of an amplifier, even after fabrication, to a desired one by means of a digital control signal and a digital to analog converter. Using this approach, the gain of basic differential amplifier is controlled by two different predistorters, and adjustable dB-linear characteristics in range of greater than 60 dB are achieved. The approach, also, is applied to two conventional VGAs, the gain characteristic of first VGA is linearized, and in the second VGA, the linear dynamic range is expanded about 26 dB. The controller uses 1.2 V voltage supply, and simulations are done using 0.13 µm CMOS process model. The other characteristics of each mode of control are reported completely.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

A new triple proximity-fed circularly polarized microstrip antenna

A novel circularly polarized microstrip antenna using triple proximity-fed method is proposed in this paper. The circular polarization radiation is produced by adjusting 120° phase shift between the feeds. In the feeding network, a three-way circular-sector power divider is adopted to distribute the current equally to each feed. A method of moments is employed for optimizing the design and achieving a good circular polarization at the center frequency of 1.28 GHz. The measured result shows that 3-dB axial ratio bandwidth and maximum gain are about 0.68% (8.7 MHz) and 7.11 dBic, respectively, which are consistent with the simulated values of 0.70% (9.0 MHz) and 7.21 dBic. The narrow bandwidth and reasonable gain indicate that this antenna is promising for various applications in L-band.     

A new CMOS differential current-mode AGC on the division operation based

A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 µm CMOS process confirm the theoretically obtained results.     

An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS

A low pass (LP) and complex band pass (CBP) reconfigurable analog baseband circuit for software-defined radio (SDR) receivers is presented. It achieves 1–15 MHz LP bandwidth, 2–8 MHz CBP bandwidth and 0–36 dB gain range with 1 dB step. Nulling-resistor Miller feed-forward (NRMFF) differential-mode compensation, passive left half-plane (LHP) zero common-mode compensation and Quasi-Floating Gate (QFG) technique are proposed to improve the high frequency performance and driving capability of the embedded fully differential operational amplifier (Op-Amp). The analog baseband circuit has been implemented in 65 nm CMOS. It achieves 15.2 dB m/27.1 dB m IB/OB-IIP3, −2 dB m IP1dB and 71 dB m IIP2 while consuming 3.6–9.1 mW from a 1.2 V power supply and 0.75 mm² chip area.