共查询到20条相似文献,搜索用时 31 毫秒
1.
《Solid-state electronics》2006,50(9-10):1515-1521
Al0.26Ga0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μHall) of 1770 cm2/Vs with a low sheet resistance (ρs) of 365 Ω/sq. (2DEG density ns = 1.0 × 1013/cm2) at room temperature compared with those of a sample without the AlN interfacial layer (μHall = 1287 cm2/Vs, ρs = 539 Ω/sq., and ns = 0.9 × 1013/cm2). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs. 相似文献
2.
K. Čičo D. Gregušová J. Kuzmík M. Jurkovič A. Alexewicz M.-A. di Forte Poisson D. Pogany G. Strasser S. Delage K. Fröhlich 《Solid-state electronics》2012,67(1):74-78
We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al2O3 gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al2O3 growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ~0.6 A/mm (VGS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al2O3 dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing. 相似文献
3.
《Microelectronics Reliability》2015,55(2):347-351
The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices. 相似文献
4.
Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to LG = 0.5 μm, LG = 0.25 μm and LG = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (ID-VGS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of ET = EV + 0.9 eV (carbon) with concentrations of NIT = 5 × 1016cm− 3, NIT = 5 × 1017cm− 3 and NIT = 5 × 1018cm− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm. 相似文献
5.
Malin Borg Eric Lefebvre Mikael Malmkvist Ludovic Desplanque Xavier Wallart Yannick Roelens Gilles Dambrine Alain Cappy Sylvain Bollaert Jan Grahn 《Solid-state electronics》2008,52(5):775-781
The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance gds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an fT of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic fT of 165 GHz and an extrinsic fmax of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic fT and fmax of 120 GHz and 110 GHz, respectively. 相似文献
6.
The microwave damage effect on high electron mobility transistor (HEMT) low noise amplifier (LNA) under different drain voltage bias is studied using TCAD simulation and experiments. Simulation and experimental results suggest that the damage power thresholds and damage locations of single stage LNA under different drain voltage bias are almost the same. Nevertheless, the output power under zero drain bias is about 5.6 dB higher than it under normal (3 V) drain bias with the injection of large power microwave pulses. In Addition, the output power relative to it under normal drain bias decreases linearly with the increase of drain bias, following the function of PdB = − 1.85Vds + 5.7. For multi-stage LNA, the observation using optical microscope reveals that the first and second stage HEMT of LNA under zero drain bias are both damaged while only first stage HEMT of LNA under normal bias is damaged with the injection of same large power microwave pulses, which is consistent with simulated output characteristics results. 相似文献
7.
David J. Smith David A. Cullen Lin Zhou Martha R. McCartney 《Microelectronics Reliability》2010,50(9-11):1514-1519
This paper reviews some of our recent studies of III-nitride high electron mobility transistor (HEMT) devices using advanced electron microscopy methods. Sample preparation protocols have been developed that can routinely provide thin, electron-transparent specimen regions of uniform thickness extending across entire HEMT devices. The use of focused-ion-beam (FIB) thinning facilitated access to specific device regions, although structural damage and imaging artifacts can result unless suitable precautions are taken during milling to minimize ion-beam damage. The extent of gallium-ion sidewall implantation during FIB milling, and surface damage caused by deposition of Pt protective layers, have been assessed. As-processed device structures have been examined by conventional diffraction contrast imaging as well as high-resolution phase contrast imaging, while nanospectroscopy and nanoscale elemental mapping have been used to measure local variations in chemical composition. Annealing of Ti/Al/Ni/Au ohmic contacts for AlInN/AlN/GaN devices lead to the formation of TiN contact inclusions that are invariably located at mixed-type threading dislocations originating from the underlying GaN layers. Some preliminary observations of device structures after extended periods of operation and after device failure have also been made. The technique of off-axis electron holography has been used to quantify two-dimensional electrostatic fields within cross-sectioned devices with nanometer-scale resolution. Polarization fields of 6.9 MV/cm and a two-dimensional electron gas of ~2.1 × 1013/cm2 have been measured for an AlInN/AlN/GaN heterostructure. Methods suitable for in situ biasing of HEMT samples during electron holography observations have also been explored. 相似文献
8.
Effect of AlN buffer layer thickness on the properties of GaN films grown by pulsed laser deposition
The GaN films are grown by pulsed laser deposition (PLD) on sapphire, AlN(30 nm)/Al2O3 and AlN(150 nm)/Al2O3, respectively. The effect of AlN buffer layer thickness on the properties of GaN films grown by PLD is investigated systematically. The characterizations reveal that as AlN buffer layer thickness increases, the surface root-mean-square (RMS) roughness of GaN film decreases from 11.5 nm to 2.3 nm, while the FWHM value of GaN film rises up from 20.28 arcmin to 84.6 arcmin and then drops to 31.8 arcmin. These results are different from the GaN films deposited by metal organic chemical vapor deposition (MOCVD) with AlN buffer layers, which shows the improvement of crystalline qualities and surface morphologies with the thickening of AlN buffer layer. The mechanism of the effect of AlN buffer layer on the growth of GaN films by PLD is hence proposed. 相似文献
9.
A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of fT=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band. 相似文献
10.
We report a comparative study of artificial neural network (ANN) model and small signal model (SSM) based on extracted parameters. ANN model training is done using Levenberg-Marquardt back propagation algorithm, whereas SSM is formed by extracting circuit parameters from measured S-parameters of GaN HEMT on Silicon and Sapphire. It has been found that, for the GaN HEMT parameter extraction, it takes 85 hidden layer neurons to produce the output with higher accuracy. The optimized test and training error/performance are found to be 1.12 × 10− 8/0.97 and 1 × 10− 8/0.99, respectively. 相似文献
11.
Malek Gassoumi Hana Mosbahi Ali Soltani Vanessa Sbrugnera-Avramovic Mohamed Ali Zaidi Christophe Gaquiere Houcine Mejri Hassen Maaref 《Materials Science in Semiconductor Processing》2013,16(6):1775-1778
AlGaN/GaN/Si high electron mobility transistors (HEMTs) grown by molecular beam epitaxy are investigated using direct-current and radio-frequency measurements. As has been found, the maximum of drain current achieves 881 mA/mm with an extrinsic current gain cutoff frequency of 37 GHz for a 0.25 µm gate length. Pulsed characteristics also showed a reduction of trapping centers that improves the quality of the epilayers. 相似文献
12.
We report the fabrication of bottom-gate thin film transistors (TFTs) at various carrier concentrations of an amorphous InGaZnO (a-IGZO) active layer from ~1016 to ~1019 cm−3, which exceeds the limit of the concentration range for a conventional active layer in a TFT. Using the Schottky TFTs configuration yielded high TFT performance with saturation mobility (μsat), threshold voltage (VTH), and on off current ratio (ION/IOFF) of 16.1 cm2/V s, −1.22 V, and 1.3×108, respectively, at the highest carrier concentration active layer of 1019 cm−3. Other carrier concentrations (<1019 cm−3) of IGZO resulted in a decrease of its work function and increase in activation energy, which changes the source/drain (S/D) contact with the active layer behavior from Schottky to quasi Ohmic, resulting in achieving conventional TFT. Hence, we successfully manipulate the barrier height between the active layer and the S/D contact by changing the carrier concentration of the active layer. Since the performance of this Schottky type TFT yielded favorable results, it is feasible to explore other high carrier concentration ternary and quaternary materials as active layers. 相似文献
13.
A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (VBR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (Cgs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the VBR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (fT) and the maximum oscillation frequency (fmax) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications. 相似文献
14.
C.P. Chen T.D. Lin Y.J. Lee Y.C. Chang M. Hong J. Kwo 《Solid-state electronics》2008,52(10):1615-1618
A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In0.2Ga0.8As on GaAs using TiN as gate metal and Ga2O3(Gd2O3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at Vg = 4 V and Vd = 2 V, a low gate leakage of <10?7 A/cm2 at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at Vg = 3 V, Vd = 2 V, and an on/off ratio of ~105 in drain current. For comparison, a TiN/Ga2O3(Gd2O3)/In0.2Ga0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10?8–10?9 A/cm2, well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ~16 and a low interfacial density of state of ~(2~6) × 1011 cm?2 eV?1, and an atomically sharp smooth Ga2O3(Gd2O3)/In0.2Ga0.8As interface. 相似文献
15.
《Microelectronics Reliability》2015,55(1):48-51
A normally-off InAlN/GaN MIS-HEMT with HfZrO2 gate insulator was realized and investigated. By using N2O plasma treatment beneath the gate region, 13 nm InAlN Schottky layer was oxidized to AlONx + 4 nm InAlN Schottky layer. The strong polarization induced carriers in traditional InAlN/GaN 2 DEG quantum well was reduced for enhancement-mode operation. High-k thin film HfZrO2 was used for gate insulator of E-mode device to further suppress gate leakage current and enhance device gate operation range. The maximum drain current of E-mode InAlN/GaN MIS-HEMT was 498 mA/mm and this value was higher than previous published InAlN/GaN E-mode devices. The measurement results of low-frequency noise also concluded that the low frequency noise is attributed to the mobility fluctuation of the channel and N2O plasma treatment did not increase fluctuation center of gate electrode. 相似文献
16.
We examined the effects of post-annealing in forming-gas ambient on the spin-on-dielectric (SOD)-buffered passivation as well as the conventional plasma-enhanced chemical vapor deposition (PECVD) Si3N4 passivation structure in association with the quantitative analysis of defects at the passivation interfaces of AlGaN/GaN high electron mobility transistors (HEMTs). Before the annealing, the interface state densities (Dit) of the PECVD Si3N4 are one-order higher (1012–1013 cm−2 eV−1) than those of the SOD SiOx (1011–1012 cm−2 eV−1) as derived from C–V characterization. Clear reduction in Dit from the PECVD Si3N4 is extracted to a level of 1011–1012 cm−2 eV−1 with a stronger absorption from Si–N peak in Fourier transform infrared spectroscopy spectra after the post-annealing. On the other hand, negligible difference in Dit value is obtained from the SOD SiOx. In this paper we propose that much lower measurement levels (~156 mA/mm) before the annealing and substantial recovery (~13% increase) after the annealing in maximum drain current density of the AlGaN/GaN HEMTs with Si3N4 passivations are due to the original higher density before the annealing and greater reduction in Dit of the PECVD Si3N4 after the annealing. Significant reduction after the annealing in gate–drain leakage current (from ~10−3 to ~10−5 A, 100-μm gate width) of the HEMTs with the Si3N4 passivation is also supposed to be attributed to the reduction of Dit. 相似文献
17.
This study demonstrated AlGaN/GaN Schottky barrier diodes (SBDs) for use in high-frequency, high-power, and high-temperature electronics applications. Four structures with various Fe doping concentrations in the buffer layers were investigated to suppress the leakage current and improve the breakdown voltage. The fabricated SBD with an Fe-doped AlGaN buffer layer of 8 × 1017 cm− 3 realized the highest on-resistance (RON) and turn-on voltage (VON) because of the memory effect of Fe diffusion. The optimal device was the SBD with an Fe-doped buffer layer of 7 × 1017 cm− 3, which exhibited a RON of 31.6 mΩ-cm2, a VON of 1.2 V, a breakdown voltage of 803 V, and a buffer breakdown voltage of 758 V. Additionally, the low-frequency noise decreased when the Fe doping concentration in the buffer layer was increased. This was because the electron density in the channel exhibited the same trend as that of the Fe doping concentration in the buffer layer. 相似文献
18.
《Applied Superconductivity》1999,6(10-12):541-545
A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO2/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (Jc up to 2×104 A/cm2) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good Vm quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO2 membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz. 相似文献
19.
G. Sonia E. Richter F. Brunner A. Denker R. Lossy M. Mai F. Lenk J. Bundesmann G. Pensl J. Schmidt U. Zeimer L. Wang K. Baskar M. Weyers J. Würfl G. Tränkle 《Solid-state electronics》2008,52(7):1011-1017
AlGaN/GaN heterostructure field effect transistors (HFETs) were irradiated with 2 MeV protons, carbon, oxygen, iron and krypton ions with fluences ranging from 1 × 109 cm?2 to 1 × 1013 cm?2. DC, pulsed I–V characteristics, loadpull and S-parameters of the AlGaN HFET devices were measured before and after irradiation. In parallel, a thick GaN reference layer was also irradiated with the same ions and was characterized by X-ray diffraction, photoluminescence, Hall measurements before and after irradiation. Small changes in the device performance were observed after irradiation with carbon and oxygen at a fluence of 5 × 1010 cm?2. Remarkable changes in device characteristics were seen at a fluence of 1 × 1012 cm?2 for carbon, oxygen, iron and krypton irradiation. Similarly, remarkable changes were also observed in the GaN layer for irradiations with fluence of 1 × 1012 cm?2. The results found on devices and on the GaN layer were compared and correlated. 相似文献
20.
《Microelectronics Reliability》2015,55(1):31-37
For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of tunnel-field effect transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5 × 1017 cm−3 and a minimum length of 20 nm enables 5 nm TFETs to exhibit favorable on–off switching characteristics. In sub-20 nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25 nm to sustain reversely biased drain voltage of 0.7 V. The asymmetric Si1−xGex source heterojunction is combined with the minimum drain design in 5 nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5 nm TFETs. 相似文献