A new CMOS class AB serial link transmitter with a low supply voltage sensitivity

This paper presents a new class AB transmitter with a low supply voltage/ground bouncing sensitivity for 10 Gb/s serial links. The low sensitivity of the output current to supply voltage fluctuation and ground bouncing is achieved by operating the system in a rail-to-rail swing mode. High data rates are obtained by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully differential configuration and bipolar signaling of the transmitter minimize the effect of both common-mode disturbances and electro-magnetic interferences exerted from channels to neighboring devices. The class AB operation of the transmitter minimizes its static power consumption. The proposed transmitter is implemented in a 1.2 V 0.13μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Both pre and post-layout simulation results demonstrate that the transmitter conveys a sufficiently large differential output current that is insensitive to supply voltage fluctuation and ground bouncing at 10 Gb/s. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering, and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Minghai Li received the B.Eng. (96) and M.A.Sc (06) degrees from North University of China and Ryerson University, Toronto, Ontario, Canada, respectively, both in Electrical and Computer Engineering. During 1996–2001, he was with Motorola Semiconductor (China) as a MCU product engineer. He was involved with MCU new product design, simulation, and test program development. He was a research assistant and a M.A.Sc student with the Microsystems Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. He is now with Micron Technology Inc., Boise, Idaho, USA as a design engineer. His research interest is in the design of CMOS mixed-signal circuits for high-speed data transmission, including multiplexer, driver, pre-emphasis, and VCOs.     

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.     

A dual complex pole-zero cancellation frequency compensation with gain-enhanced stage for three-stage amplifier

A dual complex pole-zero cancellation (DCPC) frequency compensation technique with gain enhanced stage (GES) for three-stage amplifier is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that the frequency response of three-stage amplifier exhibits that of a single-pole system. Meanwhile, the effective transconductance of output stage can be greatly increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. Thus the gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 1.23 MHz, DC gain of 111 dB, PM of 86° and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ± 1 V supply in a standard 0.6-μm CMOS technology. Qiang Li received the B.S. degree and the M.Sc. degree in College of Microelectronics and Solid-state Electronics from University of Electronic and Technology Science of China (UESTC), in 2002 and 2005, respectively. His main research interest is low-voltage low-power analog ICs and power switch management ICs. From 2005, he joined the o2micro as an analog IC designer. Jun Yi un Yi received the B.S. degree and the M.Sc. degree, both in Microelectronics, from University of Electronic Science and Technology of China, Chengdu, China, in 2001 and 2004, respectively. He is currently working toward the Ph.D. degree at The Hong Kong University of Science and Technology, Hong Kong, China. His research interests include low-voltage low-power analog and mixed-signal integrated circuits, low-power power management system, with current emphasis on ultra-low-power power management and signal processing integrated circuits for micro-sensor, RFID, and biomedical applications. Bo Zhang was born in Chongqing, China, on May 26, 1964. He received his B. Tech. degree in electronic engineering from Beijing Institute of Technology, China in 1985, the M. Tech. degree from the University of Electronic Science and Technology of China in 1988. From 1988 to 1996, he worked on power semiconductor devices research and development at the University of Electronic Science and Technology of China. From 1996 to 1999, he was a Visiting Professor at Virginia Polytechnic Institute and State University, Blacksburg, U.S.A., where his research activities include device simulations, power semiconductor cryogenics, SiC power devices, and other Si-based power semiconductor devices. Since returning to the University of Electronic Science and Technology, China, in Nov. 1999, he has worked on power devices and smart power ICs. He is currently a Professor and has published more than 100 papers in the international conferences and journals. Zhaoji Li, professor, the director of IC design center of University of Electronic Science and Technology of China (UESTC).     

基于双通路跨导运放的电压模DC/DC片内频率补偿电路

提出了一种新颖的电压模DC/DC频率补偿电路. 通过在内部跨导运放的两条小信号通路中构造阻容网络,此电路能够产生双零点以实现环路高稳定性. 由于其结构简单,易于完全集成,因此有效地减少了外围应用器件数目及印制板面积. 同时, 通过对跨导运放的优化设计进一步提高环路瞬态响应性能. 采用此电路的一款电压模DC/DC转换器已在一0.5 μm CMOS 工艺线投片,测试结果表明环路稳定性良好, 负载调整率及线性调整率均小于0.3%, 400 mA负载阶跃对应输出电压响应时间小于15 μs, 同时补偿器件面积小于裸片面积的2%, 印制板面积减小了11%. 整个芯片的效率高达95%.     

A fully integrated 2.4 GHz CMOS high power amplifier using parallel class A&B power amplifier and power-combining transformer for WiMAX application

A new structure integrated power amplifier with watt-level output power is presented in a standard 0.18 μm CMOS process for WiMAX applications. A parallel cascode class A&B power amplifier with optimized widths is proposed to increase linearity and efficiency simultaneously. A novel interleaved PCT power combiner is proposed for increasing output power that combines output current of two similar class A&B power amplifiers. Proposed interleaved transformer heightens coupling factor compared to typical transformer.     

一种低压APF和TSC并联最优运行的方法

针对低压电网中传统有源电力滤波器(APF)和晶闸管投切电容器(TSC)简单并联运行时出现的系统不稳、TSC频繁投切等问题,提出了一种基于FBD法的统一APF和TSC且共用电抗器的控制方法。该方法只通过一个控制器同时计算出APF的补偿指令电流和TSC投切组数控制信号。通过负载电流的变化率dILq/dt判断负载是否处于暂态过程,来决定是否更新TSC的投切状态,从而避免TSC的频繁投切和系统振荡。共用电抗器的拓扑结构还能节约经济成本,减小装置体积。通过仿真实验,验证了系统的可行性及有效性,是一种高性价比且性能优良的无功及谐波补偿方法。     

Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier

This study develops a post-linearization technique to simultaneously improve the input third-order intercept point (IIP3) and image-rejection ratio (IRR) of a 17 GHz low noise amplifier (LNA) in a 0.18 μm standard CMOS process. A third-order intermodulation distortion (IMD3) compensator constructed by a second-order notch filter was proposed to achieve both high linearity and image reject (IR) of the cascode LNA. The correlation between the post-linearization and IR techniques is analyzed and discussed. The measured LNA achieved a gain of 16.5 dB, a noise figure (NF) of 4.58 dB, an IIP3 of 0 dBm, and an IRR from 68 to 78 dB. The improvements of IIP3 and IRR are 11.7 and 46 dB, respectively, better than that of the LNA without the notch filter. The proposed IR LNA with total current dissipation of 4.8 mA under 1.8 V supply voltage and notch filter only dissipate a DC power of 2 mW.