Electrical and optical analyses of trapping phenomenon with temperature dependence of organic device

Carrier mechanism in actual organic devices is not simple, owing to the dielectric nature of active organic semiconductor layers, the complexity of the organic device interface, carrier trapping effects by stress biasing, and others. By coupling the conventional electrical measurement, e.g., current–voltage, capacitance–voltage and capacitance-frequency measurements, with optical charge modulation spectroscopy (CMS) measurement, we studied the hysteresis behavior and the temperature dependence of indium tin oxide/polyimide/6,13-Bis(triisopropylsilylethynyl)pentacene(TIPS-pentacene)/Au diodes to understand the effect of carrier trapping caused by injected carriers. The coupled electrical and optical measurements were very helpful to clarify carrier injection that was followed by carrier trapping in the diode, in terms of hysteresis behavior. CMS measurement was used to observe energetic states of carriers in TIPS-pentacene double-layer diode. Finally, the carrier mechanism in organic diodes was discussed by analyzing the diodes as a Maxwell-Wagner effect element.     

Decoupling the Bias‐Stress‐Induced Charge Trapping in Semiconductors and Gate‐Dielectrics of Organic Transistors Using a Double Stretched‐Exponential Formula

A novel strategy for analyzing bias‐stress effects in organic field‐effect transistors (OFETs) based on a four‐parameter double stretched‐exponential formula is reported. The formula is obtained by modifying a traditional single stretched‐exponential expression comprising two parameters (a characteristic time and a stretched‐exponential factor) that describe the bias‐stress effects. The expression yields two characteristic times and two stretched‐exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer‐side of the interface and the gate‐dielectric layer‐side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate‐dielectric layer were varied systematically. It was found that the gate‐dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias‐stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self‐assembled monolayer further widens the distribution of the activation energy for charge trapping in gate‐dielectric layer‐side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance.     

Constant Bias Stress Effects on Threshold Voltage of Pentacene Thin-Film Transistors Employing Polyvinylphenol Gate Dielectric

We investigate the stability of pentacene thin-film transistors using a poly(4-vinylphenol) (PVP) gate dielectric under constant bias stress. The threshold voltage is shifted to the positive gate voltage when stressed in air, as caused by water vapors in the PVP gate dielectric. Meanwhile, we observe a negative shift under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration 4.5 x 10¹¹ cm^-2 that is needed to avoid the critical degradation, resulting in a W/L larger than 40.     

Gate pulse electrical method to characterize hysteresis phenomena in organic field effect transistor

Hysteresis phenomena in the current–voltage characteristics of organic thin-film transistors (OTFTs) between the up and down sweeps are commonly observed. This hysteresis behavior is strongly affected by the trapping-effect. In this work, we present a new experimental technique to study these phenomena. The technique is based on the time-dependent drain current measurements as a function of a pulsed gate voltage. The decay of the drain current observed when a gate bias is applied to the gate electrode is correlated to the trapping-detrapping effects in the silicon oxide and/or at the organic semiconductor/silicon oxide interface. We show how to use this pulse gate electrical method to characterize the true device performances (threshold voltage, carrier mobility) of petacene organic field effect transistors (OFETs) with SiO₂ gate dielectric under different pulsed conditions, avoiding the pitfalls due to the presence of the hysteresis effect when using classical static data analysis methods. Moreover, we demonstrate that the charge carrier mobility is less affected by the trapping and detrapping phenomena than the threshold voltage.     

Charge Trapping in Intergrain Regions of Pentacene Thin Film Transistors

A scanning Kelvin probe microscopy (SKPM) study of the surface potential of vacuum sublimed pentacene transistors under bias stress and its correlation with the film morphology is presented. While for thicker films there are some trapping centers inhomogeneously distributed over the film, as previously reported by other authors, by decreasing the film thickness the effect of thin intergrain regions (IGRs) becomes clear and a very good correlation between the topography and the potential data is observed. It is shown that in the thick pentacene grains the potential is homogeneous and independent of the gate bias applied with negligible charge trapping, while in the thin IGRs the potential varies with the applied gate bias, indicating that only an incomplete accumulation layer can be formed. Clear evidence for preferential charge trapping in the thin IGRs is obtained.     

Fast organic thin-film transistor circuits

We have fabricated organic thin-film transistors and integrated circuits using pentacene as the active material. Devices were fabricated on glass substrates using low-temperature ion-beam sputtered silicon dioxide as the gate dielectric and a double-layer photoresist process to isolate devices. These transistors have carrier mobility near 0.5 cm²/V-s and on/off current ratio larger than 10⁷. Using a level-shifting design that allows circuits to operate over a wide range of threshold voltages, we have fabricated ring oscillators with propagation delay below 75 μs per stage, limited by the level-shifting circuitry. When driven directly, inverters without level shifting show submicrosecond rise and fall time constants     

Electrical stability of pentacene thin film transistors

The influence of environmental conditions on the device operation and the stability of polycrystalline pentacene thin film transistors (TFTs) were investigated. Electrical in-situ and ex-situ measurements of staggered pentacene TFTs were carried out to study the influence of dry oxygen and moisture on the device stability. The transistors were fabricated by organic molecular beam deposition on thermal oxide dielectrics. Oxygen exposure of the pentacene films lead to the creation of acceptor-like states in the bandgap. The acceptor-like states cause a shift of the onset of the drain current towards positive gate voltages. The charge carrier mobility and the on/off ratio of the transistor are not affected by the acceptor-like states. Furthermore, the acceptor-like states have an influence on the stability of the TFTs. Devices exposed to oxygen exhibit a shift of the threshold voltage upon prolonged biasing. Transistors characterized under vacuum conditions (no oxygen exposure) do not exhibit a shift of the threshold voltage (bias stress effect) as a consequence of prolonged biasing. The experimental results show a clear correlation between the device behavior upon oxygen exposure and the stability of the devices. The shift of the onset voltage upon oxygen exposure correlates with the shift of the threshold voltage upon prolonged bias. The influence of dry oxygen on the onset voltage, the threshold voltage, and the electrical stability will be described. Furthermore, the influence of bias stress on the operation of organic circuits like an active matrix addressed OLED displays will be discussed.     

Gate insulators and interface effects in organic thin-film transistors

This paper presents a detailed characterization of different thermosetting polymers to be used as gate dielectrics in organic thin-film transistors. Selected materials yield smooth films with good insulation properties and offer attractive processing conditions. Bottom-gate transistors were prepared using these dielectrics and compared to hybrid transistors with surface-treated SiO₂ as the dielectric. Gate bias induced leakage and solvent effects were investigated by preparing metal/insulator/semiconductor devices. Poly(3-hexylthiophene) (P3HT) transistors with organic dielectrics exhibited higher channel conductivity and lower mobility values with respect to P3HT-hybrid transistors and pentacene transistors. The importance of dielectric/semiconductor interface was discussed by comparing the performances of pentacene and P3HT transistors produced on different dielectrics.     

有机场效应晶体管最新实验研究进展

介绍了近两年新报道的有机半导体材料,列举了其场效应性能参数;综述了有机场效应晶体管(OFET)在器件结构上的改进,重点阐述了基于常见有机功能层材料富勒烯及其衍生物、并五苯、聚3-己基噻吩的OFET对栅介质层及有机功能层与电极的界面的改进,讨论了器件结构改进对OFET阈值电压、开关比、载流子迁移率的影响;介绍了衬底温度、退火处理对OF-ET性能的影响。最后,针对有机场效应晶体管研究现状,指出未来研究中应注重开发高迁移率、高薄膜稳定性的有机功能材料和高介电常数、高成膜质量的有机栅介质材料,继续优化器件结构,改进制备工艺以提高器件性能。     

The Effect of Gate‐Dielectric Surface Energy on Pentacene Morphology and Organic Field‐Effect Transistor Characteristics

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field‐effect transistors (FETs) are reported, using surface‐energy‐controllable poly(imide‐siloxane)s as gate‐dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three‐dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low‐surface‐energy gate dielectric is larger by a factor of about five, compared to their high‐surface‐energy counterparts. In pentacene growth on the low‐surface‐energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low‐surface‐energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high‐surface‐energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.     

Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High- $kappa$ Gate Dielectric

In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with gate dielectric are well investigated for the first time. Under room temperature stress condition, the. PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for LTPS-TFT. In addition, an abnormal behavior of the degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the gate dielectric and the poly-Si grain boundaries.     

High-performance pentacene thin-film transistor with ZrLaO gate dielectric passivated by fluorine incorporation

Pentacene thin-film transistor with high-κ ZrLaO gate dielectric has been fabricated for the first time. After treating the dielectric in a fluorine plasma, the carrier mobility of the transistor can be greatly improved to 0.717 cm²/V s, which is more than 40 times that of one without plasma treatment. The major reasons should be larger pentacene grains and fewer traps in the device with gate dielectric passivated by the fluorine plasma. AFM confirms that relatively large and high pentacene islands form on the plasma-treated dielectrics in the initial growth stage, and the growth pattern obviously follows the Vollmer–Weber growth model. Furthermore, the surfaces of the dielectrics with different plasma treatment times are investigated by AFM, XPS and contact-angle measurement to reveal the mechanism/effects of the fluorine incorporation. Lastly, after exposure to atmosphere without encapsulation for 6 months, all the devices still display good transistor characteristics.     

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T_phy) hafnium oxide (HfO₂)/silicon dioxide (SiO₂) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).     

Enhanced electrical and photosensing properties of pentacene organic thin-film phototransistors by modifying the gate dielectric thickness

The effects of dielectric layer thickness on the electrical performance and photosensing properties of organic pentacene thin-film transistors have been investigated. To improve the electrical performance of pentacene thin-film transistors (TFTs), the poly-4-vinylphenol (PVP) polymer with various thicknesses was used in fabrication of the pentacene transistors. The pentacene thin-film transistor with the PVP dielectric layer of 70 nm exhibited a field-effect mobility of 4.46 cm²/Vs in the saturation region, a threshold voltage of −4.0 V, a gate voltage swing of 2.1 V/decade and an on/off current ratio of 5.1 × 10⁴. In the OFF-state, the photoresponse of the transistors increases linearly with illumination intensity. The pentacene transistor with the thinner dielectric layer thickness indicates the best photosensing behavior. It is evaluated that the electrical performance and photosensing properties of pentacene thin-film transistors can be improved by using various thickness dielectric layer.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing

This paper discusses time-dependent dielectric breakdown (TDDB) in n-FETs with HfSiON gate stacks under various stress conditions. It was found that the slope of Weibull distribution of T_bd, Weibull β, changes with stress conditions, namely, DC stress, unipolar AC stress and bipolar AC stresses. On the other hand, the time evolution component of stress-induced leakage current (SILC) was not changed by these stresses. These experimental results indicate that the modulation of electron trapping/de-trapping and hole trapping/de-trapping by stress condition changes the defect size in high-k gate dielectrics. Therefore, the control of injected carrier and the characteristics of trapping can provide the steep Weibull distribution of T_bd, leading to long-term reliability in scaled CMOS devices with high-k gate stacks.     

Trapping and reliability issues in GaN-based MIS HEMTs with partially recessed gate

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al₂O₃. Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator.The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.     

Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing

In this work, influences of oxygen effect on an Hf-based high-k gate dielectric were investigated. A post deposition annealing (PDA) including oxygen ion after high-k dielectric deposition was used to improve reliability of the Hf-based high-k/metal gate device. The basic electrical characteristics of devices were compared with and without the PDA process. Experiment results show that the oxygen PDA did not degrade the drive current and effective oxide thickness of the Hf-based gate devices. In addition, reliability issues such as positive bias instability, negative bias instability and TDDB were also improved by the oxygen PDA significantly. During the TDDB test, the charge trapping was characterized by an in situ charge pumping system, which could make us to understand the variations of interface trap during the reliability stress easily.     

Effects of film microstructure on the bias stability of pentacene field-effect transistors

In this report, the effects of film microstructure on the bias stability of pentacene field-effect transistors (FETs) were investigated. To control the microstructure of pentacene film, substrate temperature was changed from 25 to 90 °C during pentacene deposition. As the substrate temperature increased, pentacene grain size increased (or grain boundary (GB) decreased) because of the elevated surface diffusion of pentacene molecules. Accordingly, field-effect mobility increased up to 1.52 cm²/V. In contrast, bias stability showed totally different characteristics: samples prepared at high substrate temperatures exhibited the lowest degree of bias stability. This GB independent charge trapping phenomenon was solved by examining molecular scale ordering within the intragrain regions. The pentacene film grown at 90 °C showed the largest percentage of pentacene molecules with bulk crystalline structures. This inhomogeneity in the pentacene microstructure induces crystal mismatch within intragrain region, thereby providing deep trap sites for gate-bias stress driven instability. Our study shows that GB is not the main sites for bias stress related charge trapping, rather the molecular orientation within intragrain region is responsible for the charge trapping events. In this regard, the control of molecular scale ordering is important to obtain OFETs with a high bias stability.     

Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ_FE> 1 cm²V⁻¹s⁻¹) and excellent stability under gate bias stress (bias stress V_ds = 0V). However, after prolonged bias stress performed at high drain voltage, V_ds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V_ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.