Design,fabrication and characterization of miniature RF MEMS switched capacitor based phase shifter

This paper aims to present in detail the design, fabrication and the various characterization techniques adopted in realizing a novel miniature-size switched capacitor based phase shifter. The work strives to provide an all-round development of a DMTL (Distributed MEMS Transmission Line) based phase shifting unit yielding an overall phase shift of 15° at a frequency of 15 GHz. The RF MEMS (Radio Frequency Micro Electro Mechanical Systems) Switched Capacitor based phase shifter has highly miniaturized dimensions, and is capable of solving many limitations to which the conventional Switched Capacitors are mostly susceptible. This miniature RF MEMS switched capacitor actuates at a low actuation voltage of 12 V, exhibits a fundamental frequency of vibration as high as 1.468 MHz and a switching time of 1.4 µs which is an improvement over the other reported designs. Various characterization results seem to validate the simulations.     

Design and analysis of implantable CPW fed bowtie antenna for ISM band applications

A novel implantable coplanar waveguide (CPW) fed crossed bowtie antenna is proposed for short-range biomedical applications. The antenna is designed to resonate at 2.45 GHz, one of the industrial-scientific-medical (ISM) bands. It is investigated by use of the method of moments design equations and its simulation software (IE3D version 15). The size of the antenna is 371.8 mm³ (26 mm × 22 mm × 0.65 mm). The simulated and analyzed return losses are −23 and −25 dB at the resonant frequency of 2.45 GHz. We have analyzed some more performances of the proposed antenna and the results show that the proposed antenna is a perfect candidate for implantation. The proposed antenna has substantial merits like low profile, miniaturization, lower return loss and better impedance matching with high gain over other implanted antennas.     

Design of novel wideband reflective phase shifters with wide range of phase applications

This paper presents wideband compact differential reflective phase shifter based on the double layer slot-coupled coupler configuration. This novel phase shifter arrangement consists of a 3-dB hybrid coupler with the coupled and transmission ports terminated with rectangular and elliptically shaped microstrip loads. By altering the ports termination of the coupler, phase shifters propose differential phase ranging from −90° to +90° over 1.3–5.9G Hz frequency band. To achieve different range of phase performance, the proper reactance is calculated at the outputs of coupler. These reactances are transformed to the elliptical or rectangular-shaped microstrip load with various dimensions for every phase shifter. The calculation and simulations results show that the developed circuits could provide ±30°, ±60°, ±45° and ±90° differential phase shifts. For verification of this wideband phase shifter design method, two phase shifter example with rectangular and elliptical load termination is fabricated and measured. The measured return loss of the phase shifter with elliptically load is better than 10 dB over 1.3–5.9G Hz frequency band as well as insertion loss is less than 1 dB. The phase shift deviation is less than 2.1°. The results demonstrate that the proposed phase shifters are well suited for use in GPS/LTE/WiMax/WLAN frequency bands.     

A compact broadband MMIC sub-harmonic mixer using quasi-lumped transmission lines

A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70 nm GaAs mHEMT technology is demonstrated for 60 GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5×0.77 mm². The conversion gain is optimized by a quasi-lumped 90° phase shift stub. Experimental results show that from 50 GHz to 70 GHz, the conversion gain varies between −12.1 dB and −15.2 dB with a LO power level of 10 dBm and 1 GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5 dB, 21.3 dB and 25.8 dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1 dB compression point of -2 dBm and exhibits outstanding figure-of-merits.     

A miniaturized Vivaldi antenna by loading with parasitic patch and lumped resistor

A miniaturized Vivaldi antenna is presented in the paper. On the basis of original antenna, the miniaturized Vivaldi antenna applies parasitic patch and lumped resistor to improve impedance characteristics. The proposed load can expand the lower operating frequency to 1.96 GHz without changing antenna dimensions. The size of antenna is set as 43 × 40 mm². This size is about 0.28λ_L × 0.26λ_L, where λ_L is the free space wavelength at 1.96 GHz. The loaded Vivaldi antenna is fabricated and measured. The simulated and measured results clarify the viability and effectiveness of the proposed design. The measured impedance bandwidth (VSWR ≤ 2) is from 2 GHz to more than 18 GHz. In addition, the measured radiation patterns and a peak gain between −1 and 9 dB can be obtained in the band of 2–18 GHz.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

A printed monopole ellipzoidal UWB antenna with four band rejection characteristics

An antenna design with four band rejection characteristics for UWB application is demonstrated. The proposed unique UWB antenna has shape of an embedded ellipse at top of trapezoidal patch (named as ellipzoidal), 50 Ω impedance microstrip line feed and a truncated beveled ground plane. To realize four band stop characteristics, three inverted U-shaped and a single I-shaped slots each of half guided wavelength are utilized on radiating element. The fabricated antenna has dimensions of 27 mm × 36 mm × 1.6 mm. This four band notched ellipzoidal UWB antenna has measured frequency bandwidth 2.8–14 GHz for magnitude of S₁₁ < −10 dB level. The measured ellipzoidal antenna exhibits four band rejection characteristics for magnitude of S₁₁ > −10 dB at 3.55 GHz for WiMAX band (3.26–3.9 GHz), 4.55 GHz for ARN band (4.35–5.05 GHz), 5.7 GHz for WLAN band (5.5–6.65 GHz) and 8.8 GHz for ITU-8 band (7.95–9.35 GHz). The proposed ellipzoidal UWB antenna maintains omnidirectional radiation pattern, gain, linear phase response, <1 ns group delay, and transfer function in the whole UWB operating bandwidth except at notched frequency bands.     

Distributed NGD active circuit for RF-microwave communication

This paper is aimed to the investigation on innovative distributed negative group delay (DNGD) circuits for RF communication. Thanks to the analogy between the lumped and distributed circuits, NGD circuit topologies were identified. By using the S-parameter theory, analysis and synthesis methods of these topologies are proposed. The DNGD circuits developed are mainly comprised of a transistor combined with a series resistance ended by a stub. Then, synthesis relations enabling to determine the NGD circuit parameters from the desired NGD and gain values are established. As application, an active phase shifter (PS) operating independently with the frequency based on the cascade of PGD and NGD devices was synthesized. First, an NGD PS with transmission phase of (135 ± 5)° around 2.56 GHz over the bandwidth of about 1.02 GHz was obtained. Then, a two-stage DNGD PS exhibiting 90° with ±10° flatness from 4.1 GHz to 6.8 GHz was designed. The DNGD circuit presented can be used in various telecommunication areas notably for correcting RF/numerical signal delays in the RF-microwave analogue-digital devices.     

Corrugated SIW K band horn antenna

In the recent years, the strong demand for high performance, low cost and high gain antennas for telecommunication, surveillance, and imaging applications has rapidly grown at microwave and higher frequencies. High speed wireless links require modular, compact size and high directivity with low cross polarization antennas. To demonstrate the proposed concepts and design features, in this paper, a substrate integrated waveguide (SIW) feeding technique has been created having well behaved gain and suitable −10 dB bandwidth from 23.8 GHz to 25.7 GHz (roughly 2 GHz bandwidth), while the impedance bandwidth for VSWR < 2.5 is nearly 3 GHz. The simulated antenna attains 12.5 ± 1 dB gain over majority of K band with an occupied size of 82 mm × 40 mm × 2.54 mm and has roughly 95% radiation efficiency. The proposed antenna is an excellent candidate for integrated low cost K band and even higher frequency systems. The simulations are done by two full wave packages i.e. ANSYS HFSS and CST MWS that associated with finite element method (FEM) and finite difference time domain (FDTD), respectively. The results show good agreements between these two methods.     

Life test of an X-band MMIC multi-function chip for active phased array radar applications

A 1000-h steady state life test at a temperature of 125 °C was performed on ten X-band MMIC multifunction chips for use in active phase array radar systems. Internal switches, phase shifters, and attenuators were operated through an integrated serial-to-parallel converter under the five-second stepped external control signal for the life test period. None of the ten samples failed under the failure criteria based on the JEP118 standard. The calculated failure rate using the Chi Square Statistic was 1.6 e⁻⁶ failures/h for the 90% confidence level. Maximum DC current variation was +16% for an initial value. Maximum variations of small signal gain, phase shift, and attenuation were 0.96 dB, 2°, and 0.17 dB, respectively, over a frequency range of 8.5–10.5 GHz.     

A planar waveguide optical discrete Fourier transformer design for 160 Gb/s all-optical OFDM systems

A cost-effective all-optical discrete Fourier transformer (ODFT) is designed based on a silicon planar lightwave circuit (PLC), which can be applied to all-optical orthogonal frequency division multiplexing (OFDM) transmission systems and can be achieved by current techniques. It consists of 2 × 2 directional couplers, phase shifters and optical delay lines. Metal-film heaters are used as phase shifters, according to the thermooptic effect of SiO₂. Based on the ODFT, a 160 Gb/s OFDM system is set up. Simulation results show excellent bit error rate (BER) and optical signal-to-noise ratio (OSNR) performances after 400 km transmission.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

Multiband monopole antenna loaded with Complementary Split Ring Resonator and C-shaped slots

This paper presents a compact semi circular monopole antenna loaded with Complementary Split Ring Resonator (CSRR) and two C-shaped slots is proposed for Global System for Mobile Communication (GSM), Worldwide Interoperability for Microwave Access (WiMAX) and C-band applications. The size of the proposed antenna is 20 × 20 × 0.5 mm³. The resonance frequency of WiMAX (3.73 GHz) is achieved by introducing CSRR slots on the ground plane. To realize multiband characteristics for GSM (1.77 GHz), WiMAX (2.6 GHz) and C-band (4.15 GHz), two C-shaped slots of quarter wavelength are introduced in radiating element. The extraction procedure of negative permittivity for the proposed CSRR is discussed in detail. The proposed antenna is fabricated and measured. Simulated and measured results are in good agreement. Omni directional radiation pattern is obtained in H-plane and bi directional radiation pattern is obtained in E-plane. Parametric study of CSRR and C-shaped slot are examined to obtain best results. The proposed antenna has significant advantages, including low profile, miniaturization ability, and good impedance matching.     

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called extended statistical element selection to achieve best-in-class HR ratio (HRR) performance. The achieved concurrent 3rd order HRR and 5th order HRR are greater than 80 dB and 70 dB, respectively, after calibration. The even order HRR is also calibrated to greater than 80 dB. A single calibration performed at 750 MHz was further observed to be effective over more than two octaves of bandwidth with greater than 70 dB HRR. The receiver was manufactured in 65 nm CMOS technology. Input RF frequency range was 0.15–1 GHz and the receiver consumes 64 mW at 1 GHz. Noise figure is 3.2 dB and out-of-band IIP3 is −7 dBm at a total gain of 48 dB.     

RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications

In this paper a radio frequency (RF) to direct current (DC) voltage converter with multi-stage rectifiers is reported for micro power conversion in RF power harvesting systems. The purpose of this paper is to select an appropriate structure for the micro power-converters, operating in high frequencies. The main idea is to convert RF range sinusoidal signals to a DC voltage to produce power for the rest of the electrical circuit or a system. The reported rectifier demonstrated an efficiency of 10% at large span of frequency for input signal of 350 mV. In the presented work, an analytical and numerical study of the micro power-converters is reported for various applications. Different design parameters have been investigated for an efficient structure design including, number of MOSs, DC current of a known load, size of MOSFETs capacitors, and frequency of the operation. Consequently, optimized parameters have been reported in order to improve the RF to DC conversion efficiency. Reported circuits were designed and simulated in 180 nm twin-well CMOS process with low threshold metal-oxide semiconductor field-effect transistors (MOSFETS); this multistage rectifier occupied an area of 0.23 mm × 0.146 mm and it produced an output voltage of 2 V at its output. This output voltage can provide the supply voltage required to operate the RFID processing circuitry. Post layout simulations demonstrated that for thirteen stages of the rectifiers, the efficiency of 10% for a capacitive load of 10 pF has been achieved.     

115 Gbit/s downstream and 10 Gbit/s upstream TWDM-PON together with 11.25 Gbit/s wireless signal utilizing OFDM-QAM modulation

In this work, we propose and investigate a 115 Gbit/s (4 × 28.75 Gbit/s) downstream and 10 Gbit/s upstream time- and wavelength-division-multiplexing passive optical network (TWDM-PON) together with 11.25 Gbit/s wireless broadcasting signal using multi-band orthogonal-frequency-division-multiplexing (OFDM) modulation within 10 GHz bandwidth. Here, to compensate the power fading and chromatic dispersion in the higher frequency, we utilize a −0.7 chirp parameter Mach–Zehnder modulator (MZM) for the OFDM signal. Hence, negative power penalties of −0.3 and −0.4 dB in the downstream and broadcasting wireless signals; and power penalty of 0.3 dB in the upstream signal are measured at the bit error rate (BER) of 3.8 × 10⁻³ after 20 km standard single mode fiber transmission without dispersion compensation.     

UWB Metamaterial-based miniaturized planar monopole antennas

In this paper, ultra wide band (UWB) metamterial based compact planar antennas have been designed and experimentally verified. Four novel unit cells have been realized and each unit cell dispersion characteristics are numerically calculated which follows CRLH-TL properties. These four CRLH-TL unit cells are loaded into monopole antennas which result, four open-ended MTM antennas respectively. Further, a novel via free version of CRLH-TL unit cells have been designed, which increases the fabrication flexibility. The compactness has been achieved by realizing ZOR (zeroth order resonance) mode and its bandwidth is increased by realizing small shunt capacitance and large shunt inductance. Further, by optimizing CRLH-TL unit cells, two closely spaced zeroth-order and first-order resonance modes are merged into a single pass band, which gives wide bandwidth. The each proposed antenna has a compact dimension of 0.27 λ₀ × 0.19 λ₀ × 0.02 λ₀ (22 × 15 × 1.6 mm³), where λ₀ is a free space wavelength at 3.8 GHz. The four proposed antennas have S₁₁ < −10 dB impedance bandwidths of 8.4 GHz, 8.5 GHz, 8.2 GHz and 8.3 GHz respectively. The optimum gain, good efficiency, desired radiation characteristics in frequency domain analysis and less distortion of waves in time domain analysis have been achieved for proposed antennas, which are most suitable for UWB applications. The CST-MWS has been used for the parametric study of the proposed antennas. A good agreement has been observed between simulated and experimental results.     

An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications

This paper presents a Sub-mW differential Common-Gate Low Noise Amplifier (CGLNA) for ZigBee standard. The circuit takes the advantage of shunt feedback and Dual Capacitive Cross Coupling (DCCC) to reduce power consumption and the bandwidth extension capacitors to support 2.4 GHz ISM band. An amplifier employing these techniques has been designed and simulated in 0.18 µm TSMC CMOS technology. The Simulation results show a gain of 18.2 dB, an IIP3 of −4.32 dBm and a noise figure of 3.38 dB at 2.4 GHz. The proposed LNA consumes only 967 µW from a 1-V supply.     

A tunable CMOS Wilkinson power divider using active inductors

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.     

Dual-resonance concurrent oscillator

This paper studies a new dual-band CMOS class-C voltage-controlled oscillator (VCO). The oscillator consists of a dual-resonance LC resonator in shunt with two pairs of capacitive cross-coupled nMOSFETs. The proposed oscillator has been implemented with the TSMC 0.18 μm CMOS technology, and it shows a frequency tuning range with two frequency bands and a small tuning hysteresis is measured. The oscillator can generate differential signals at 2.4 GHz and 6.9 GHz and it also can generate concurrent frequency oscillation while the circuit is biased around the bias with frequency tuning hysteresis. With the supply voltage of V_DD = 1.1 V, the VCO-core current and power consumption of the oscillator are 2.90 mA and 3.19 mW, respectively. The die area of the class-C oscillator is 0.9 × 0.97 mm². Overvoltage stress is applied to the oscillator, measurement indicates the concurrent oscillation is sensitive to overvoltage stress.