Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.     

Analysis of multistage amplifiers with hybrid cascode feedforward compensation using a modified model for load impedance

Hybrid cascode feedforward compensation (HCFC) is an effective technique to stabilize nano-scale three-stage amplifiers driving ultra-large load capacitors. It divides the compensation capacitance and shares it between two high-speed local feedback loops embedded within the amplifier core. In this article, a systematic approach to analyze the transfer function and to evaluate the pole expressions of nano-scale HCFC amplifiers is presented. For the first time, the equivalent output impedance is successfully modeled to approximate the complicated transfer function of the HCFC amplifier without the need for lengthy pencil-and-paper calculations. An HCFC amplifier is designed and simulated in 90-nm CMOS technology, to verify the effectiveness of the new analytic approach. The simulated transfer function of the amplifier is almost identical to a calculated transfer function derived based on the new model.     

基于动态频率补偿的LDO电路设计

文中提出了一种基于动态频率补偿技术的LDO电路。通过添加电压缓冲器,提高了LDO的环路增益和瞬态响应特性。该电路通过电流镜采样调整管电流,使主极点频率与第三极点频率随负载电流的改变而产生相同倍数的变化,克服了LDO零极点随负载变化而导致环路稳定性变差的问题。文中设计采用中电二十四所HC12.BJT工艺,利用Spectre仿真工具进行仿真,研究了不同负载电流下该LDO的频率特性及其稳定性问题。仿真结果表明,该电路在10 μA~100 mA负载电流的变化范围内,LDO环路的相位裕度保持在50°~70°之间,证明提出的LDO调整器具有良好的稳定性。     

一种新的应用于开关电容DC/DC转换器的补偿电路

采用Chartered 0.35μm CMOS工艺,设计实现了输入电压范围2.7～5.5 V,负载电流高达200mA的降压式开关电容型DC/DC转换器.为了在整个输入电压和负载电流范围内稳定输出电压,并且提高输出电压精确度,在对开关电容转换器环路建模分析后,提出了一个新的应用于开关电容DC/DC转换器的频率补偿电路.该...     

Basic considerations and topologies of switched-mode assistedlinear power amplifiers

This paper presents a combined power amplifier system consisting of a linear amplifier unit with a switched-mode (class D) current dumping stage arranged in parallel. With this topology, the fundamental drawback of conventional linear power amplifiers-the high loss-is avoided. Compared to a pure class D (switching) amplifier, the presented system needs no output filter to reduce the switching frequency harmonics. This filter (usually of multistage type) generally deteriorates the transient response of the system and impairs the feedback loop design. Furthermore, the low-frequency distortions of switching amplifiers caused by the interlock delay of their power transistors are avoided with the presented switched-mode assisted linear amplifier system. This can be considered as a master-slave system with a guiding linear amplifier and a supporting class D slave unit. The paper describes the operating principle of the system, analyzes the fundamental relationships for the circuit design, and presents simulation results. Finally, various further topologies of switched-mode assisted linear amplifiers are given     

Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.     

基于高开关频率精确模型的峰值电流型BUCK电源的补偿设计

针对工作在高开关频率的连续导电模式的峰值电流型BUCK电压源,建立了包含功率管导通电阻和寄生参数的精确小信号模型,设计一个新颖的电压环路的补偿模块,优化了瞬态响应。补偿模块仅增加一个极点,消除输出电容寄生电阻引入的零点。在此补偿模块基础上,分析了输出电压Vo对参考电压Vref的传递函数的频率响应,和补偿模块直流增益之间的关系,得出了补偿模块的最佳增益,使得输出电压对参考电压Vref的瞬态响应既快速又没有过冲和振荡,并且在Spice电路仿真中得到验证。     

电流型PWM DC-DC升压转换器的稳定性分析与实现

文章先对影响电流型DC-DC升压转换器电路的系统稳定性的因素进行分析，然后在电路设计实现上提出了具体的改进办法：在误差放大器模块增加频率补偿电路来消除放大器反馈环路可能存在的振荡现象：采用斜坡补偿电路来增强反馈电流环路的稳定；为了提高电压反馈环路的稳定性，创新提出在芯片外部增加COMP管脚。内部增加环路补偿电路；输入管脚增加旁路电容以减少噪声；输出管脚增加旁路电容以增强芯片反馈系统的稳定性;通过采取这些措施，保证了芯片电路的的稳定性能，并极大的提高了输出电压的精度，设计取得了很大成功。     

Admittance Compensation in Current Loop Control for a Grid-Tie LCL Fuel Cell Inverter

Current loop transfer function of a single-phase grid-tie inverter has been systematically derived with representations of conventional transfer function format using admittance terms for controller design and loop compensation. The power circuit adopts the LCL type filter to allow universal output that can be operated in both standalone and grid-tie modes. The proposed admittance compensation along with a quasi-proportional-resonant controller is designed to achieve high gain at the fundamental frequency while maintaining enough stability margins. The entire current loop controller and admittance compensation have been simulated and tested with a 5-kW fuel cell prototype. Without the admittance path compensation, simulation results indicate that the system cannot start up smoothly and the zero current command cannot be tracked very well. At first simulation cycle, the power flow erratically fed back to the inverter that may cause catastrophe failure. With admittance path compensation, the time-domain current steady-state error can be easily reduced with the loop gain design in frequency-domain. Simulation and experimental results show that the inverter is capable of both standalone and grid-tie connection mode operations and smooth power flow control even with zero current command.      

A novel active compensation scheme for active-RC filters

A novel scheme using two internally compensated operational amplifiers with unmatched gain-bandwidth products is suggested as a replacement for the conventional single-amplifier integrators, inverters or summers. The scheme, while providing exact phase compensation, contributes to magnitude compensation as well. Filters realized using such a scheme have an extended range of frequency of operation with reduced error in pole frequency and in Q.     

Stabilizing High Order Sigma Delta Modulators by Time Delay Feedback Technique

Second and high order sigma delta modulators (SDM) have been extensively used in data conversion processes since their high resolution. However it is difficult to stabilize second and high order SDM over a wide signal range because of the integrals output saturation. A time delay compensation has been proposed in this paper in order to stabilize high order SDM by keeping the integrators output signal levels below saturation limits most of time. The proposed compensation technique is very simple and contains two design parameters; time delay element and compensation gain. It has been shown that high mode jumping leads integrator clipping can be prevented by tuning the compensation design parameters. Particularly w-domain describing function has been employed to tune compensation gain for desired mode/modes in the closed loop. The effect of the compensation gain has been graphically monitored for a constant delay time. Furthermore, the effect of compensation on overall signal-to-noise ratio (SNR) has also been discussed. The proposed compensation technique can be implemented to various configurations of oversampling converters; single-loop and multiple-loop.     

共源共栅两级运放的三种补偿结构分析和比较

提出了三种应用于两级CMOS运算放大器的米勒电容补偿结构,分析了三种结构的小信号等效电路,得到传递函数和零点、极点的位置,以此分析和实现三种结构的频率补偿。其中两种共源共栅米勒补偿结构与直接米勒补偿结构相比,能用更小的芯片面积实现更优的运放性能,得到更大的单位增益带宽积和相位裕度,实现更好的频率特性。通过使用0.18μm CMOS工艺对电路进行仿真,结果验证了共源共栅米勒补偿技术的优越性。     

电流模PWM降压DC_DC片内补偿电路的设计实现

对单片电流模降压DC_DC的内部电流环与电压环的稳定性进行了分析研究,分别采用分段线性斜坡补偿与内置频率补偿技术,有效消除环路亚谐波振荡并克服了稳定性对输出负载以及误差放大器增益的依赖,提高了芯片的瞬态响应速度及输出带负载能力。采用TSMC0.25μmBCD工艺设计实现了一款高电压电流模PWM降压型的DC_DC芯片,spectre仿真结果表明,输出电流可达2A,其线性调整率和负载调整率均小于0.3%,输出电压对负载1A时的阶跃响应时间小于70μs。     

降压型DC-DC转换器自调节型斜坡补偿电路设计

本文给出一种用于降压型DC-DC转换器的自调节型斜坡补偿电路。文章从斜坡补偿的基本原理出发,根据电流环稳定的条件,设计出了一种补偿量随输入输出电压自动调节的斜坡补偿电路。该斜坡补偿电路的优化设计避免了因过补偿而带来的系统瞬态响应慢和带载能力低等不良影响。该电路基于华润上华0.5um CMOS工艺,使用Cadence仿真验证达到设计目标。     

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.     

Large bandwidth BiCMOS operational amplifiers for SC videoapplications

A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm² and 0.96 mm² for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V     

High speed sample and hold design using closed-loop pole-zero cancelation

A new closed loop Sample-and-Hold (S&H) architecture is proposed for pipeline analog-to-digital converter (ADC) that breaks the precision-speed-power trade off by means of canceling out the first closed loop pole. This pole-canceling results in widening the bandwidth of the S&H up to the second pole. In this architecture, two amplifiers are used: one for accuracy with little power consumption, another one for high-speed response, which consumes most of the total power. Exploiting these two amplifiers remedies some of the tradeoffs and limitations of opamp design in S&H circuits. Simulated by HSPICE with a standard BSIM3v3 0.13 μm technology, the S&H achieves 80 dB SFDR for a 1.6 V_ppd output at 500 MHz sampling rate.     

极点跟随的LDO稳压器频率补偿方法

提出了一种新型的用于LDO稳压器的频率补偿方法,并通过动态偏置电压缓冲器进行了电路实现。该方法提供了快速的瞬态响应,且无需芯片上频率补偿电容,提高了芯片的集成度。理论分析与仿真结果表明,LDO稳压器在满负载条件下的频率稳定得到了保证。     

Note on two integrator loop OTA-C configurations

A two integrator loop structure with six operational transconductance amplifiers (OTAs) and two capacitors has been proposed by Sanchez-Sinencio, et al. (1988). However, the filter functions which can be provided by this general architecture have not been available to date, although its special four OTA and two OTA derivatives have been studied. It is demonstrated that this circuit, with voltages applied to the input terminals of the OTAs inside the loops and output voltages from the circuit nodes inside the loops, offers many very useful and interesting functions such as LP, BP, HP, BS, LPN, HPN and AP without using floating capacitors, coefficient difference nulling and additional OTAs. Other existing two integrator loop structures cannot offer all the functions under similar conditions     

压电式推力测试系统动态性能分析与改善

姿控火箭发动机推力测试系统的动态性能对于推力测量的准确性具有重要影响.采用方形脉冲力模拟发动机推力,对压电式推力测试系统进行了动态标定,根据频响特性曲线建立了测试系统的高阶传递函数模型并获得了动态性能指标.针对测试过程中的超调和振荡,基于高阶传递函数模型,采用阻尼补偿法对推力测试系统的输出进行补偿.结果表明,经过补偿后误差减小,改善了压电式推力测试系统的动态性能.