过孔阻抗控制及其对信号完整性的影响

传输线的连续性问题是高速数字电路设计的重点,尤其是高速多层PCB中的过孔结构。随频率的增加和上升时间的缩短,过孔阻抗不连续、寄生电容和电感会引起信号反射和衰减,并导致信号完整性问题。本研究采用矢量网络分析仪研究了单端微带线上过孔孔径、焊盘、反焊盘大小对阻抗连续性的影响,并通过为过孔信号提供返回路径,提高了过孔阻抗连续性与信号完整性。     

分割单元对电源/地平面输入阻抗影响的研究

研究了在多层印制电路板电源/地平面过孔周围布置具有桥接结构的蚀刻分割单元时过孔信号的返回路径阻抗及转移阻抗。分析了分割单元尺寸变化对返回路径阻抗的影响。采用二维边界元法进行了数值分析,并通过全波有限元分析软件进行了仿真验证。研究结果表明,在频率较高时,分割单元会激发较多的谐振峰值,返回路径阻抗大幅上升,但有助于降低噪声耦合。     

高速PCB单端过孔研究

在高速数字电路设计中,过孔的寄生电容、电感的影响不能忽略,过孔在传输路径上表现为阻抗不连续的断点,会产生信号的反射、延时、衰减等信号完整性问题。文章采用矢量网络分析仪研究了过孔长度、过孔孔径、焊盘/反焊盘直径对过孔阻抗的影响。通过在信号孔旁增加接地孔,为过孔电流提供回路方法,提高过孔阻抗的连续性,并有效降低过孔损耗。此外,文章还探讨了过孔多余短柱对过孔阻抗及损耗的影响。本研究可为高速数字电路过孔设计和优化提供依据。     

电流返回路径分解的信号完整性分析方法

提出了一种适用于高速互连电路的信号完整性快速仿真方法。根据电流返回路径 不同,该方法将有过孔的三维互连结构分解为电源平面对阻抗模型和微带线模型,先单独分 析两种模型特性,再级联以求解整个互连结构特性。与全波仿真方法相比,本方法在保证准 确度的前提下可将仿真时间从95 min降低至1 min以内。分析了电路板参数、去耦电容和短 路孔对信号完整性的影响,结果表明插入损耗由电源平面结构在过孔位置处的自阻抗决定。 在工程设计中,可采用减小电源平面对结构厚度、添加去耦电容和选择适当的过孔位置等方 法提高信号完整性     

高速信号过孔对信号影响因素研究

影响信号完整性的因素有很多,其中过孔结构对信号影响越来越明显,如何进行有效的过孔设计从而使过孔阻抗与激励源阻抗配从而达到信号完整性已经成为当今PCB设计业界中的一个热门课题。文章通过Ansys公司的HFSS仿真软件,利用仿真方法分析不同信号过孔结构对高速信号的影响,并对过孔残桩长度（stub）,反焊盘,焊盘的不同大小对信号差损影响程度做了进一步研究。     

过孔结构对电源分配系统性能的影响研究

针对某基于FPGA的高速高密度控制板,研究了过孔结构对电源纹波的影响。分析过孔内径、焊盘和反焊盘对目标阻抗的影响,仿真计算电源分配系统中不同过孔结构下的电源纹波,实现控制板电源完整性优化,给出最佳的过孔结构设计方案。研究结果表明:过孔结构的不同将引起电源分配系统性能的变化,在走线安全距离的范围内,孔内径和焊盘直径越大,电源纹波越小,电源纹波从–10.0%~2.4%优化为–8.85%~1.14%。     

参考平面转换对信号传输的影响及传输优化

在多层印刷电路板(PCB)设计时,经常需要信号通过过孔跨接到其他层走线,这种走线方式会导致返回路径不连续(RPD),引发信号完整性问题,文中应用电磁场全波仿真工具SIwave构建信号跨层走线模型,从电源分配网络(PDN)阻抗的角度分析了跨层走线对信号传输的影响,同时使用添加电容的方法优化信号传输路径,并对电容的选取及其位置的确定进行了研究,为PCB设计提供参考。     

过孔转换信号完整性分析的区域分解有限元法

提出了一种基于区域分解的二维有限元法分析多层印制电路板电源/地平面中过孔转换结构的信号完整性.过孔电流产生的电磁场呈三维结构,其中,一部分电磁波沿过孔轴向传输,另一部分电磁波在电源/地平面间沿径向传播.采用一虚拟柱面将求解区域分割为过孔区和电源/地平面区.将过孔区建模为以周向磁场为主分量的二维轴对称问题,而将电源/地平面区建为以垂直电场为主分量的二维模型.首先求解电源/地平面区的二维边值问题获得分割边界上节点的波阻抗,然后将该波阻抗代入过孔区模型中分割边界节点的边界条件,从而计算出过孔信号传输的S参数.所提方法通过模型缩减可实现对微细过孔结构信号完整性的精确快速计算,且采用全波电磁场分析软件对算法的有效性和准确性进行了验证.     

差分过孔的高频特性仿真分析

为满足差分过孔在高速PCB中低反射、高传输和阻抗稳定的设计要求,提出了短柱和非功能焊盘的优化设计方法,并给出了建模仿真与理论分析。采用HFSS软件对12层PCB中差分过孔进行三维建模与仿真,并使用ADS软件对仿真结果进行了眼图分析,结果表明:钻除短柱可以有效改善差分过孔的高频传输特性,其中信号反射的能量减少了79.1%,传输的能量增加了82.1%;移除非功能焊盘可以进一步改善差分过孔的高频特性,其中反射的能量减少了14.46%,传输的能量增加了14.13%。     

FC-CBGA封装中高速差分信号过孔的设计与优化

对FC-CBGA封装中高速差分信号过孔的设计与优化问题进行研究,分析了采用堆叠孔、增加地回流孔和增大过孔反焊盘尺寸这三种优化方法对减小电容和电感不连续性,以提高过孔电性能的具体影响.时频域仿真验证了所述优化方法能够有效降低高速差分信号插入损耗及回波损耗,提高信号过孔阻抗,改善高速差分信号传输性能.     

光模块中刚柔线路板电连接宽带阻抗匹配研究

文章分别对光收发组件中50 Ω柔性线路板和50 Ω刚性线路板,以及25Ω柔性线路板和50Ω刚性线路板间的电互连阻抗匹配进行了设计、仿真与实验验证.对于50 Ω_50 Ω刚柔板的高频连接,通过对其返回路径的通孔位置优化设计,使反射损耗Su在高频段降低约11％,插入损耗S21减小190％;对于25 Ω_50 Ω刚柔板的高频连接,提出新的优化方式:在硬板信号线的金手指上做通孔设计,并提取该结构的寄生参数,构建电路模型.该结构大幅提高了连接处容性阻抗,降低了阻抗失配,使得S11在高频段降低约38.2％,S21减小约34％.提出的柔性线路板与刚性线路板的电互连方式,能实现传输线间的阻抗匹配,减小信号反射和插入损耗,提高光模块传输质量,对于光器件的接入具有较大应用价值.     

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus     

Lumped-circuit model extraction for vias in multilayer substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.     

A Semi-Analytical Approach for System-Level Electrical Modeling of Electronic Packages With Large Number of Vias

This paper presents a semi-analytical approach for electrical performance modeling of complex electronic packages with multiple power/ground planes and large number of vias. The method is based on the modal expansion technique and the method of moments. For the inner package domain with multiple power/ground planes and many vias, the modal expansion method is employed to compute the electromagnetic fields from which the multiport network parameters, e.g., the admittance matrix can be easily obtained. For the top/bottom domain of signal layers, the moment method is used to extract the equivalent resistance, inductance, capacitance, and conductance (RLCG) parameters. The equivalent circuit for the entire package is then generated by combining the results for both package domains. The equivalent circuit can be used in a SPICE-like simulator to study the signal and power integrity of an electronic package. Numerical examples demonstrate that the new approach is able to provide fast yet accurate signal and power integrity analysis of multilayered electronic packages.     

Modeling and Measurement of Radiated Field Emission From a Power/Ground Plane Cavity Edge Excited by a Through-Hole Signal Via Based on a Balanced TLM and Via Coupling Model

A balanced transmission line model (TLM) and via coupling model is proposed for efficient simulation of radiated field emission from a power/ground plane cavity edge, where the radiated field emission is excited by a through-hole signal via in a multilayer package and printed circuit board (PCB). The radiated field emission is simulated and measured with a series of test boards. The simulation agrees fairly well with the measurement confirming the preciseness and usefulness of the proposed model. It is shown that the through-hole signal via is a considerable source of the radiated field emission as well as the signal loss. When the signal trace is switching vertically stacked reference planes, the signal return current path is disconnected at the via and the impedance becomes extremely high. A significant amount of insertion loss and radiated field emission is generated at resonance frequencies of the plane cavity. The effect of a decoupling capacitor fence (De-Cap Fence) at the edge of the board to mitigate the radiated field emission is examined. The proposed model confirms that the De-Cap Fence changes the resonance mode and frequency of the plane cavity, and reduces the radiated field emission