A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer’s knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

A Smart Power Integrated Circuit Educational Tool

This paper describes a course in Smart Power based on the introduction of an innovative educational tool-a preprocessed Smart Power integrated circuit. The methodology used to introduce students to the issue of Smart Power design, resorting to low cost standard CMOS technology is presented. The theoretical support is envisaged to provide the required knowledge to specify characteristics and performance of the most common blocks used in Smart Power and to develop skills for monolithic integration. Through design, simulation, and experimental characterization, the students were able to experience the different steps of a Smart Power project, from the power device basic switching cell mask layout to the final system prototype, in 60 hours of a one semester course. The referred Smart Power Integrated Circuit (IC) embedding analog and digital basic blocks and high-voltage transistor arrays is the key idea to the presented pedagogical methodology. Based on this Smart Power IC, different topologies required by power electronics and power management systems were implemented. A complete system illustrative example-a step-down hard-switching dc-dc regulator (buck regulator)-implemented by the students is shown and discussed.     

Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

An evaluation of deep-submicron CMOS design optimized for operation at 77 K

Using a careful and insightful analysis of the possible benefits of 77 K CMOS in submicron technology from a decade ago [1], the development of 77 K CMOS in present-day deep submicron technology is evaluated. It is found that the basic principles from the earlier study—that the real benefit of 77 K CMOS operation is the ability to provide “pure” scaling of the threshold voltage and thus to allow aggressive super-scaling of MOS transistor dimensions—not only holds in present-day CMOS processes, but is even more important in that regard. A detailed analysis of CMOS technology, digital circuit behavior, and analog circuit behavior is provided. It is noted that not only does properly-designed 77 K CMOS technology provide opportunities; it also addresses some of the most fundamental difficulties facing CMOS technology and CMOS circuit design.     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Generation of accurate on-chip time constants and stabletransconductances

A method for generating accurately known on-chip time constants and less accurate but stable transistor transconductances over process, power-supply, and temperature variations is presented. The technique uses a constant-g_m bias circuit, which has a resistor that is tuned with a fully integrated CMOS phase-locked loop (PLL) locked to an external frequency reference (normally present in most systems). Other on-chip analog circuits biased using the same constant-g_m bias circuit are also stabilized. The PLL uses a charge-pump structure with three control loops (two digital and one analog) having overlapping ranges with hysteresis to minimize tuning glitches in the steady state. The PLL has a lock range of 135 to 300 MHz, and displays an RMS jitter of 15.6 ps. The transconductances generated from the circuit display a 2.2% variation for a 60°C change in temperature, and a 1.3% variation for a 10% variation in power-supply voltage. The design has been fabricated in a 0.35-μm CMOS process, using an active area of 1200×1200 μm² and draws 5.8 mA from a 3.3-V supply     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Automatic Scaling Procedures for Analog Design Reuse

In this paper, a methodology for analog design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances g_m and output conductances g_DS. If g_m's and gDS's of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-mum, 2.5-V voltage supply to a 0.15-mum, 1.2-V voltage supply in standard CMOS technologies     

Causal reasoning mining approach to analog circuit verification

Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification (Barke et al. [1]), focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications (Jiao et al., 2015 [2]). Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.     

An artificial intelligence approach to active filter synthesis

This paper deals with a novel active filter synthesis method using artificial intelligence (AI). The AI-based synthesis methodology uses original analog circuit representation performed by a Prolog backward-chaining inference mechanism. Circuit representation is specified as an analog circuit language to describe filter topologies, performance characteristics, and subcircuits. Synthesis is organized as a Prolog searching program based on backward-chaining strategy to transform input specifications into an appropriate filter structure. The Prolog program performs symbolic equation transformations to proper filter transfer characteristics. The proposed synthesis methodology has been developed for integrated continuous-time filter structures using operational transconductance amplifiers and capacitors to realize tunable and active C filters. A synthesis program has been implemented in Turbo Prolog on an IBM PC AT computer, and a filter example is presented demonstrating the use of the program.This paper was supported by the Ministry of Education of Poland Grant CPBP 02.14.     

Constraint transformation for IC physical design

In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications