Distributed diagnosis for homogeneous systems

This article presents a distributed fault-diagnosis algorithm for identifying faulty and fault-free units (processors, PEs, cells) in homogeneous systems. It is based on local comparison among units in a system and dissemination of the test results. Each unit performs comparison with its neighbors by using its own comparator. Unlike other approaches, the algorithm does not assume that diagnostic circuits are fault free. The algorithm is simple enough to be realized with small circuit overhead. The results are especially useful in locating faulty units in processor arrays implemented on a single chip or wafer. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be obtained by adjusting algorithm parameters.     

Test Generation Algorithm for Linear Systems Based on Genetic Algorithm

This paper proposes a test generation algorithm combining genetic algorithm for fault diagnosis on linear systems. Most test generation algorithms just used a single value fault model. This test generation algorithm is based on a continuous fault model. This algorithm can improve the treatment of the tolerance problem, including the tolerances of both normal and fault parameters, and enhance the fault coverage rate. The genetic algorithm can be used to choose the characteristic values. The genetic algorithm can enhance precision of test generation algorithm especially for complex fitness functions derived from complex systems under test. The genetic algorithm can also further improve the fault coverage rate by reducing the loop number of divisions of the initial fault range. The experiments are carried out to show this test generation algorithm with a linear system and an integrated circuit.     

An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism

At present, functional verification represents the most expensive part of the digital systems design. Moreover, different problems such as: clock synchronization, code compatibility, simulation automation, new design methodologies, proper use of coverage metrics, among others represent challenges in this area. The automated test vector generation is involved in these problems. In this work, an automated functional test sequences generation for digital systems based on the use of coverage models and a binary Particle Swarm Optimization algorithm with a reinitialization mechanism (BPSOr) is described. Also, a comparison with other meta-heuristic algorithms such as: Genetic algorithms (GA) and pseudo-random generation is presented using different fitness functions, coverage models and devices under verification. The main strategy is based on the combination of the simulation and meta-heuristic algorithms to test the device behavior through the generation of test vector sequences. According to the results, the proposed test generation method represents a good alternative to increase the functional coverage during the automated functional verification of block-level digital systems verification.     

Testing Methods for PUF-Based Secure Key Storage Circuits

Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. It investigates two secure Built-In Self-Test (BIST) solutions for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The schemes target high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The first scheme reuses existing FE blocks (for pattern generation and compression) to minimize the area overhead, while the second scheme tests all the FE blocks simultaneously to minimize the test time. The schemes are integrated in FE design and simulated; the results show that for the first test scheme, a SAF fault coverage of 95 % can be realized with no more than 47.1k clock cycles at the cost of a negligible area overhead of only 2.2 %; while for the second test scheme a SAF fault coverage of 95 % can be realized with 3.5k clock cycles at the cost of 18.6 % area overhead. Higher fault coverages are possible to realize at extra cost (i.e., either by extending the test time, or by adding extra hardware, or a combination of both).     

A bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs

In this paper, a novel bitstream readback-based test and diagnosis method including a bitstream parsing algorithm as well as a corresponding bitstream readback-based fault and diagnosis algorithm for Xilinx FPGAs is presented. The proposed method can be applied to both configurable logic block (CLB) and interconnect resource (IR) test. Further, the algorithm is suitable for all Virtex and Spartan series FPGAs. The issues such as fault coverage, diagnostic resolution, I/O numbers, as well as configuration numbers not addressed well by some previous works can be solved or partly relieved. The proposed method is evaluated by testing several Xilinx series FPGAs, and experimental results are provided.     

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.     

面向中继通信的空地协同无人机编队控制算法设计与仿真

随着无人机(UAV)应用场景的不断丰富,近年来利用无人机编队实现空地协同的任务日益增多。根据现阶段的编队体系和控制方法,该文设计一种基于行为策略的空地协同无人机编队控制算法：通过引入空地协同思想,为地面移动用户提供中继通信服务,扩大了无人机编队的通信覆盖范围。为7架无人机组成的编队设计了4种无人机队形,推导相应的单位中心站位标准,并使用Unity软件对空地协同无人机编队控制算法进行仿真,测试使用该算法的无人机编队在理想环境下的转弯性能和模拟实际环境下的避障、中继通信以及队形变化能力。基于所提出的空地协同算法,设计了两种任务方案：区域搜索覆盖主任务方案和用户失联搜救应急方案。实验仿真证明了改进的空地协同无人机编队控制算法及两种方案具有可行性。     

Comparison-based diagnosis with faulty comparators

The letter deals with a new approach to diagnosis by comparison. A new class of diagnosable systems is introduced: in these systems, units and comparators used in the diagnostic process may fail. Failure of comparators introduces a new condition of test invalidation for comparison. Characterisation theorems and fault identification similarities between different comparison models are presented.     

An Efficient In-Place VLSI Architecture for Viterbi Algorithm

This paper presents a novel design of Viterbi decoder based on in-place state metric update and hybrid survivor path management. By exploiting the in-place computation feature of the Viterbi algorithm, the proposed design methodology can result in high-speed and modular architectures suitable for those Viterbi applications with large constraint length. This feature is not only applied to the design of highly regular ACS units, but also exploited in the design of trace-back units for the first time. The proposed hybrid survivor path management based on the combination of register-exchange and trace-back schemes cannot only reduce the number of memory operations, but also the size of memory required. Compared with the general hybrid trace-back structure, the overhead of register-exchange circuit in our architecture is significantly less. Therefore, the proposed architecture can find promising applications in digital communication systems where high-speed large state Viterbi decoders are desirable.     

Fast fault-tolerant digital convolution using a polynomial residuenumber system

A fault-tolerant convolution algorithm that is an extension of residue-number-system fault-tolerance schemes applied to polynomial rings is described. The algorithm is suitable for implementation on multiprocessor systems and is able to concurrently mask processor failures. A fast algorithm based on long division for detecting and correcting multiple processor failures is presented. Moduli polynomials that yield an efficient and robust fast-Fourier transform (FFT)-based algorithm are selected. For this implementation, a single fault detection and correction is studied, and a generalized-likelihood-ratio test is applied to optimally detect system failures in the presence of computational noise. The coding scheme is capable of protecting over 90% of the computation involved in convolution. Parts not covered by the scheme are assumed to be protected via triple modular redundancy. This hybrid approach can detect and correct any single system failure with as little as 70% overhead, compared with 200% needed for a system fully protected via modular redundancy     

两种联邦滤波系统级故障检测方案对比与仿真

从联邦滤波的故障检测特点出发,以SINS/GPS/ADS/TACAN/RADAR组合导航系统为对象,对基于量测一致性和残差χ2检测的两级故障检测法、双状态递推故障检测法两种系统级故障检测方案进行了较为详细的分析比较,并通过预设故障模型进行了仿真.仿真结果表明:故障检测部分的加入可有效地提高多传感器组合导航系统的容错性和可靠性.两种检测方案对软、硬故障都有较高的灵敏度,但都不同程度出现误警和漏检情况,总体而言,基于量测一致性和残差χ2检测的检测方案更有优势.     

Subspace based blind identification of LTI FIR MIMO systems and equalization of finite memory SIMO Volterra systems

In this paper a novel algorithm based on subspace projections is developed for the blind kernel identification of LTI FIR multiple input multiple output (MIMO) systems, as well as blind equalization of finite memory SIMO Volterra systems. In addition, for Volterra systems, the algorithm computes the memory lengths of the nonlinearities involved. Simulations in the context of blind channel equalization and identification demonstrate good performance in comparison to existing schemes.     

Scan Test Response Compaction Combined with Diagnosis Capabilities

As today’s process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to ‘X’ tolerance and aliasing.     

Voting Techniques for Fault Diagnosis from Frequency-Domain Test-Data

The basic voting technique, which estimates the posterior fault-probability from prior fault-probability plus test data, is developed from first principles and given a pattern-recognition interpretation. This leads to the philosophy that the technique is one of a family suitable for fault diagnosis, if necessary down to component level, using only input-output frequency-domain test-data. A simulation of 39 200 faulty 7-component passive circuits is described, which shows that the two voting techniques considered in detail are superior to previously reported template-matching methods of fault diagnosis by factors of 5:1 or more in situations where nonfaulty components are permitted to have standard deviations of 3% nominal value, which is not untypical of much current practice. The circuit model is similar to modules making up larger systems of several hundred components. Because voting techniques require relatively little storage of data they are well suited to quality control schemes based on automatic test equipment. In comparison, data storage for template-matching methods are often prohibitive. Best use of voting techniques is possible when clearly defined fault cases are established which should ideally be considered at the system design stage.     

Translation of specification units between IP and ATM quality of service declarations

An integral part of any network quality of service (QoS) system are its QoS declarations. QoS declarations consist of service classes, parameters, and specification units. QoS declarations are a component of the QoS architecture, as such they are a source of heterogeneity stemming from the fact that different QoS systems may be based on different QoS architectures and thus use different QoS declarations. A particular problem in that domain is the translation of specification units for QoS systems that are based on different forwarding technologies with respect to variable vs fixed packet sizes, i.e. packet vs cell switching. This is a problem that can be dealt with generically such that its solution can be applied to several situations of technically heterogeneous QoS systems like an RSVP/IntServ—or DiffServ—over an ATM‐based system. While straightforward translations have been proposed, we investigate how more efficient translations can be achieved by using a slight but effective modification of existing AAL framing schemes as well as making use of statistical knowledge about packet size distributions. Copyright © 2003 John Wiley & Sons, Ltd.     

Cooperative Multiuser Relay Communications Employing Hierarchical Modulation

Relay-assisted cooperative communications are a promising solution for error-performance improvement and cell coverage extension. However, additional resources such as time slots or frequency bands are required for the relay, which reduce the overall throughput. This paper proposes two cooperative relay schemes that employ hierarchical modulation to overcome this limitation. One scheme is for symmetric downlink communications and the other is for asymmetric downlink communications. These schemes exploit the hierarchical modulation symbols for users in the network and allow the system to transmit two or more independent data streams simultaneously. The proposed schemes reduce the number of transmission phases to the same as conventional schemes without diversity gain. The symbol-error rates of the proposed systems are a function of the distance parameter of hierarchical modulation. By flexibly controlling the distance parameter based on specific scenarios, it allows an extra degree of freedom to guarantee error performance of receivers whose signals undergo different losses.     

矢量网络分析仪电子校准件设计与实现

为深入研究矢量网络分析仪校准技术,促进电子校准件低成本、通用化应用,基于通用的射频开关模块和开源的Arduino 控制模块搭建了电子校准件硬件系统;为适应电子校准件的非理想工作状态,基于分式变换特性推导了系统误差项的求解算法。最后利用E5071C 矢量网络分析仪和商用E4431B 电子校准件搭建对比测试系统,并选用移动通信滤波器作为测试对象,验证了所设计电子校准件硬件的正确性和误差修正算法的有效性。此研究成果可为电子校准件低成本、通用化应用提供参考。     

Analysis of LEO, MEO, and GEO global mobile satellite systems inthe presence of interference and fading

Several multisatellite and multispot systems have been recently proposed for provision of mobile and personal services with global coverage, adopting GEO or non-GEO (i.e., MEO, LEO) satellite constellations. The paper addresses an in-depth analysis of these constellations, evaluating both geometrical performance measures and cochannel interference levels caused by extensive frequency reuse. The geometrical analysis yields the statistics for coverage, frequency of satellite hand-overs, and link absence periods. The interference analysis is based on a general model valid for all access techniques, which is here applied to the case of FDMA. The outage probability as a function of the specification on carrier-to-interference power ratio is evaluated for four selected constellations. Several techniques are introduced for interference reduction in non-GEO systems, in which the satellites coverage areas may intersect: spot turnoff, intraorbital plane frequency division, and interorbital plane frequency division. The effects of Rice fading have also been analyzed by means of an analytic approximated method. The overall analysis allows a fair comparison between LEO, MEO, and GEO constellations     

基于指令生成约束的RISC-V测试序列生成方法

为了避免处理器受到指令缺陷的威胁,该文提出基于指令生成约束的RISC-V测试序列生成方法,构建测试指令序列生成框架,实现测试指令生成及指令缺陷检测,解决现有测试指令序列生成方法约束定义困难和收敛速度慢的问题。在该方法中,首先,根据指令集架构规范和指令验证需求定义指令生成约束,包括指令格式约束、通用功能覆盖约束和特殊功能覆盖约束,以解决随着指令数量增多约束定义的困难,提高可复用性;然后,定义启发式搜索策略,通过统计覆盖信息,加快覆盖率收敛速度;最后,基于启发式搜索策略构造求解算法,实现满足指令生成约束的测试序列生成。实验结果表明,与现有方法相比,在覆盖所有指令验证需求的前提下,结构覆盖率和数值覆盖率的收敛时间分别减少了85.62%和57.64%。利用该框架对开源处理器进行检测,可以定位到在处理器译码和执行阶段引入的指令缺陷,为处理器指令缺陷检测提供了有效的方法。     

A Classical Parameter Identification Method and?a?Modern Test Generation Algorithm

Many methods have been presented for the testing and diagnosis of analog circuits. Each of these methods has its advantages and disadvantages. In this paper we propose a novel sensitivity analysis algorithm for the classical parameter identification method and a continuous fault model for the modern test generation algorithm, and we compare the characteristics of these methods. At present, parameter identification based on the component connection model (CCM) cannot ensure that the diagnostic equation is optimal. The sensitivity analysis algorithm proposed in this paper can choose the optimal set of trees to construct an optimal CCM diagnostic equation, and enhance the diagnostic precision. But nowadays increasing attention is being paid to test generation algorithms. Most test generation algorithms use a single value in the fault model. But the single values cannot substitute for the actual faults that may occur, because the possible faulty values vary over a continuous range. To solve this problem, this paper presents a continuous fault model for the test generation algorithm which has a continuous range of parameters. The test generation algorithm with this model can improve the treatment of the tolerance problem, including the tolerances of both normal and faulty parameters, and enhance the fault coverage rate. The two methods can be applied in different situations.