磷硅玻璃膜的等离子活性淀积及特性

研究了由等离子体活化反应系统(P—PSG)淀积的磷硅玻离膜。分析了对应不同淀积参数的P—PSG的基本特征。在该等离子体淀积方法中,利用反应气体SiH_4、PH_3和N_2O进行淀积, P—PSG有高的淀积速率〔大约为百分之10(W/O)P摩尔重量〕。用这种方法淀积的P-PSG膜与常压下(AP-PSG)淀积的常规PSG膜比较,显示出良好的薄膜性能,如在热处理期间具有较强的抗裂性,保真的台阶覆盖和可控的压应力等。     

CeO_2高K栅介质薄膜的制备工艺及其电学性质

研究了 Ce O2 作为高 K (高介电常数 )栅介质薄膜的制备工艺 ,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用 N离子轰击氮化 Si衬底表面工艺对 Ce O2 薄膜的生长及其与 Si界面结构特征的影响 ,利用脉冲激光淀积方法在 Si(10 0 )衬底生长了具有 (10 0 )和 (111)取向的 Ce O2 外延薄膜 ;研究了 N离子轰击氮化 Si衬底表面处理工艺对 Pt/ Ce O2 / Si结构电学性质的影响 .研究结果显示 ,利用 N离子轰击氮化 Si表面 /界面工艺不仅影响 Ce O2 薄膜的生长结构 ,还可以改善 Ce O2 与 Si界面的电学性质     

用逐层淀积法制备a－Si∶H薄膜

本文用逐层淀积法制备了ａ－Ｓｉ：Ｈ薄膜，研究了生长速率、子层厚度及氢等离子体处理对薄膜性质的影响，结果指出：不同条件下的氢等离子体处理不仅可以使淀积的样品发生从非晶到微晶的相变，而且可以使费米能级的位置向上或者向下移动，在较低的淀积速率及较小的子层厚度下淀积，并配合以适度的氢等离子体处理，可以得到具有较高光电灵敏度及稳定性的ａ－Ｓｉ：Ｈ薄膜。     

用逐层淀积法制备a—Si：H薄膜

本文用逐层淀积法制备了ａ－Ｓｉ：Ｈ薄膜，研究了生长速率、子层厚度及氢等离子体处理对薄膜性质的影响，结果指出：不同条件下的氢等离子体处理不仅可以使淀积的样品发生从非晶到微晶的相变，而且可以使费米能级的位置向上或者向下移动。在较低的淀积速率及较小的子层厚度下淀积，并配合以适度的氢等离子体处理，可以得到具有较高光电灵敏度及稳定性的ａ－Ｓｉ：Ｈ薄膜。     

SiN钝化对InGaAs/InP双异质结双极性晶体管直流性能的影响

研究了SiN钝化对InGaAs/InP双异质结双极性晶体管(DHBT)直流性能的影响。在不同温度和不同气体组分条件下淀积了SiN薄膜,并对钝化器件的性能进行了测量和比较。结果表明,低的淀积温度有利于减小淀积过程对器件的损伤;采用氮气(N_2)和硅烷(SiH_4)取代常用的氨气(NH_3)和硅烷(SiH_4)作为淀积SiN薄膜的反应气体,显著地减少了器件发射结(B-E)和集电结(B-C)泄漏电流。另外,与未钝化器件的直流性能相比,钝化后器件的电流增益增加,基区表面复合电流大幅减小,这对提高器件的可靠性至关重要。     

CeO2高K栅介质薄膜的制备工艺及其电学性质

研究了CeO2作为高K(高介电常数)栅介质薄膜的制备工艺,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用N离子轰击氮化Si衬底表面工艺对CeO2薄膜的生长及其与Si界面结构特征的影响,利用脉冲激光淀积方法在Si(100)衬底生长了具有(100)和(111)取向的CeO2外延薄膜;研究了N离子轰击氮化Si衬底表面处理工艺对Pt/CeO2/Si结构电学性质的影响.研究结果显示,利用N离子轰击氮化Si表面/界面工艺不仅影响CeO2薄膜的生长结构,还可以改善CeO2与Si界面的电学性质.     

超薄硅基介质膜的制备技术与表征方法研究

在等离子体增强化学气相淀积(PECVD)系统中,采用等离子体氧化和等离子体氮化的方法,在单晶硅表面上成功制备厚度小于10nm的超薄硅基介质膜。通过X射线光电子谱(XPS)分析了超薄介质膜的化学结构,利用椭圆偏振仪测量了厚度以及折射率,同时对超薄介质膜进行了电容电压(C-V)和电流电压(I-V)特性的测量,研究其电学性质,探讨了C-V测量模式对超薄介质膜性质表征的影响,最后对两种介质膜的优缺点进行了比较。     

CeO2高K栅介质薄膜的制备工艺及其电学性质

研究了CeO2作为高K（高介电常数）栅介质薄膜的制备工艺,深入分析了衬底温度,淀积速率,氧化压等工艺条件和利用N离子轰击氧化Si衬底表面工艺对CeO2薄膜的生长及其与Si界面结构特征的影响,利用脉冲激光淀积方法在Si(100)衬底生成了具有（100）和（111）取向的CeO2外延薄膜,研究了N离子轰击氮化Si衬底表面处理工艺对Pt/CeO2/Si结构电学性质的影响,研究结果显示,利用N离子轰击氮化Si表面／界面工艺不仅影响CeO2薄膜的生长结构,还可以改善CeO2与Si界面的电学性质。     

气体流量比对PECVD硅化钛薄膜性质的影响

本文报道了以四氯化钛(TiCl_4)和硅烷(SiH_4)为源物质,采用等离子增强化学气相淀积工艺(PECVD)制备硅化钛薄膜的方法;着重研究了气体流量比变化对薄膜电阻率、淀积速率以及化学组成的影响,通过实验获得了制备优良硅化钛薄膜的最佳气流比条件。     

OLD诊断SiH_4的LPCVD动力学过程

用光声激光偏转(OLD)测量了强TEA CO_2脉冲激光辐照SiH_4-H_2系统产生等离子体淀积(LPCVD)硅薄膜过程中的激波效应,证明激光击穿SiH_4诱发的激波效应是LPCVD中基本的气体动力学过程,并讨论了激波对膜生长的影响。     

Low-frequency noise characterization of n- and p-MOSFET's withultrathin oxynitride gate films

MOSFET's with ultrathin (5 to 8.5 nm) silicon oxynitride gate film prepared by low-pressure rapid thermal chemical vapor deposition (RTCVD) using SiH₄, N₂O and NH₃ gases, are studied by low-frequency noise measurements (1 Hz up to 5 kHz). The analysis takes into account the correlated mobility fluctuations induced by those of the interfacial oxide charge. The nitrogen concentration, determined from SIMS analysis, varies from 0 to 11% atomic percentage. A comparison of the electrical properties between thermal and silicon oxynitride films is presented. The increasing LF noise signal with nitrogen atomic percentage indicates the presence of a higher density of slow interface traps with increasing nitrogen incorporation. Besides, a higher Coulomb scattering rate due to the nitridation induced interface charge explains reasonably well the degradation of the low field mobility after nitridation     

Selective oxidation technologies for high density MOS

Selective oxidation technologies using various thicknesses of silicon nitride formed by low-pressure chemical vapor deposition (LPCVD), plasma assisted nitridation in ammonia, and by nitrogen ion implantation were investigated. The transition region ("bird's beak") profiles were found to be related to the rigidity of the nitride film and also the oxidation underneath the nitride film via the buffer oxide or even a native oxide. With complete elimination of any oxide between Si3N4and Si achieved by implanting with nitrogen ions or nitriding in an ammonia plasma, a very abrupt transition region was achieved. This new sealed interface localized oxidation (SILO) technology appears to have low crystal defect density suitable for VLSI MOS technology.     

NH3与H2之比对碳纳米尖端阵列形成的影响

以CH4,NH3和H2为反应气体,利用等离子体增强热丝化学气相沉积系统在沉积有碳膜的Si上制备了碳纳米尖端阵列.利用原子力显微镜和扫描电子显微镜分别对碳膜和碳纳米尖端进行了研究,发现碳膜的表面粗糙不平,有许多凸起,在NH3与H2的比例为1/7和1/1时,可形成碳纳米尖端阵列,利用有关等离子体刻蚀理论对碳纳米尖端阵列的形成进行了分析,结果表明,只有在这两个比例下,离子对碳膜内凸起两侧有相同的溅射刻蚀速率,因此可形成碳纳米尖端阵列.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Novel interface nitridation process for thin gate oxides

A thin (100-200-Å) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories     

Optimization of saturation current density of PECVD SiN coated phosphorus diffused emitters using neural network modeling

Emitter surface passivation by low temperature plasma enhanced chemical vapor deposition (PECVD) silicon nitride is investigated and optimized in this paper. We have found that the saturation current density of a 90±10 μ/sq phosphorus diffused emitter with N_s ≈3 x 10¹⁹ and X_j ≈0.3 μm can be lowered by a factor of eight by appropriate PECVD silicon nitride deposition and photoassisted anneal. PECVD silicon nitride deposition alone reduces the emitter saturation density (J_oe) by about a factor of two to three, and a subsequent photoanneal at temperatures ≥350°C reduces J_oe by another factor of three. In spite of the larger flat band shift for direct PECVD silicon nitride coating, the silicon nitride induced surface passivation is found to be about a factor of two inferior to the thermal oxide plus PECVD silicon nitride passivation due to higher interface state density at the SiN/SiO₂ interface compared to SiO₂/Si interface. A combination of statistical experimental design and neural network modeling is used to show quantitatively that lower radio frequency power, higher substrate temperature, and higher reactor pressure during the PECVD deposition can reduce the J_oe of the silicon nitride coated emitter.     

The metal-insulator-semiconductor-switch (MISS) device using thermal nitride film as the tunneling insulator

Silicon thermal nitride films grown by using direct thermal nitridation of silicon have been used as a tunneling insulator in the metal-insulator-semiconductor-switch (MISS) device. This paper has shown that better uniformity and controllability of the MISS characteristics can be easily obtained by using thermal nitride film as a tunneling insulator when compared to those using conventional thermal oxide film. The superior merits of using silicon thermal nitride film are mainly due to the fact that direct thermal nitridation of silicon in ammonia gas exhibits much lower growth rate and unique self-limiting growth. Moreover, the higher structure density of the as-grown thermal nitride film may provide higher endurance for the MISS device in integrated-circuit applications. In addition, the MISS devices operated at lower voltage (< 5 V) have been fabricated and their characteristics are discussed.     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

快速热氮化SiO_2膜陷阱特性的研究

本文采用雪崩热电子注入技术研究了快速热氯化SiO_2膜和氮化后再氧化SiO_2膜的体电子陷阱和界面态特性。揭示出电子陷阱的起源和放电机理;观察并解释了界面态密度随氮化时间以及平带电压漂移随注入时间的变化关系;提出降低体电子陷阱密度和界面态密度的有效途径。     

多晶硅薄膜晶体管的表面氮钝化技术

采用N2O和NH3等离子钝化技术对多晶硅薄膜表面和栅氧表面进行了钝化处理。实验结果表明,该技术能有效降低多晶硅薄膜的界面态密度,提高多晶硅薄膜晶体管性能,二次离子质谱分析表明在p-Si/SiO界面有氮原子富积,说明生成了强的Si-N键。