A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.     

The effect of post-oxygen-implant annealing temperature on the channel mobilities of CMOS devices in oxygen-implanted silicon-on-insulator structures

The effects of post-oxygen-implant annealing temperature on the characteristics of MOSFET's in oxygen-implanted silicon-on-insulator (SOI) substrates are studied. The results show significant improvements in the electron and hole mobilities near the silicon/buried-oxide interface and in the electron mobility of the front-gate n-channel transistors in SOI substrates with higher post-oxygen-implant annealing temperature. The improvements in the transistor characteristics hence are attributed to the annihilation of oxygen precipitates and the reduction of defect density in the residual silicon film. By comparing the ring oscillators fabricated in SOI substrates annealed at 1150°C and 1250°C after oxygen implantation, a speed improvement of 15 percent is observed in substrates annealed at higher temperature.     

Universality of electron mobility curves in MOSFETs: a Monte Carlostudy

The universal behavior of electron mobility when plotted versus the effective field is physically studied. Due to charged centers in the silicon bulk, the oxide, and the interface, Coulomb scattering is shown to be responsible for the deviation of mobility curves. Silicon bulk-impurities have a double effect: (a) Coulomb scattering due to the charge of these impurities themselves, and (b) reduction of screening caused by the loss of inversion charge when the depletion charge is increased. The electric-field region in which mobility curves behave universally regardless of bulk-impurity concentration, substrate bias, or interface charge has been determined for state-of-the-art MOSFETs. Finally, this study shows that electron mobility must be a function of the inversion and the depletion charges rather than a simple function of the effective field     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

Comment on A. Agarwal and S. Haney, “Some Critical Materials and Processing Issues in SiC Power Devices” [J. Electron. Mater. 37, 646 (2008)]

Agarwal and Haney [J. Electron. Mater. 37, 646 (2008)] have recently suggested that bulk defects may limit the inversion-layer mobility in SiC metal oxide semiconductor field-effect transistors. However, we believe that the physics of charge trapping and Coulomb scattering by bulk traps quantitatively contradicts this model.     

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric

An inversion-channel electron mobility model for InGaAs n-channel metal–oxide-semiconductor field-effect transistors (nMOSFETs) with stacked gate dielectric is established by considering scattering mechanisms of bulk scattering, Coulomb scattering of interface charges, interface-roughness scattering, especially remote Coulomb scattering and remote interface-roughness scattering. The simulation results are in good agreement with the experimental data. The effects of device parameters on degradation of electron mobility, e.g. interface roughness, dielectric constant and thickness of high-k layer/interlayer, and the doping concentration in the channel, are discussed. It is revealed that a tradeoff among the device parameters has to be performed to get high electron mobility with keeping good other electrical properties of devices.     

On the modeling of surface roughness limited mobility in SOI MOSFETs and its correlation to the transistor effective field

In this paper, we discuss in detail the modeling of surface roughness (SR) scattering in single- and double-gate silicon-on-insulator (SOI) MOSFETs, where the conventional formulation based on the expected value of the electric field cannot be used. By reconsidering the Ando's original approach, we show that a model based on the eigenfunction derivatives at the Si-oxide interface can be naturally extended to SOI MOSFETs, and, furthermore, we also derive a formulation based on appropriate integrals of the eigenfunctions in the silicon film, which must replace the expected value of the field used in bulk MOSFETs. All the analytical identities used in the derivation of the model have been verified by using numerically calculated eigenvalues and wavefunctions. Our results indicate that, in ultrathin-film SOI MOSFETs, the effective field is no longer a good metric for the SR scattering and, furthermore, SR scattering affects the total mobility even at lower inversion densities than it does in bulk transistors.     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

A model for analyzing the interface properties of asemiconductor-insulator-semiconductor structure. I. Capacitance andconductance techniques

A model is presented for analyzing the interface properties of a semiconductor-insulator-semiconductor (SIS) capacitor structure. By introducing a coupling factor, conventional metal-oxide-semiconductor (MOS) capacitor theory is extended to analyze the interface properties of the film/buried-oxide/substrate interfaces of a silicon-on-insulator (SOI) material. This model was used to determine parameters such as doping concentration, buried oxide thickness, fixed oxide charge, and interface trap density from the SIMOX (separation by implantation of oxygen) based SIS capacitors     

Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs

A rigorous surface-roughness scattering model for ultrathin-body silicon-on-insulator (SOI) MOSFETs is derived, which reduces to Ando's model in the limit of bulk MOSFETs. The matrix element of the scattering potential reflects the fluctuations of both the wavefunction and the potential energy. The matrix element reflecting the fluctuation of the wavefunction is expressed in an integral form which can be considered as a generalized Prange-Nee term-to which it is equivalent in the limit of an infinitely high insulator-semiconductor barrier-giving more accurate results in the case of a finite barrier height. The matrix element reflecting the fluctuation of the potential energy is due to the Coulomb interactions originating from the roughness-induced fluctuation of the electron charge density, the interface polarization charge, and the image-charge density. The roughness-limited low-field electron mobility in thin-body SOI MOSFETs is obtained using the matrix elements that we have derived. We study its dependence on the silicon body thickness, effective field, and dielectric constant of the insulator.     

Monte Carlo simulation of electron transport properties inextremely thin SOI MOSFET's

Electron mobility in extremely thin-film silicon-on-insulator (SOI) MOSFET's has been simulated. A quantum mechanical calculation is implemented to evaluate the spatial and energy distribution of the electrons. Once the electron distribution is known, the effect of a drift electric field parallel to the Si-SiO₂ interfaces is considered. The Boltzmann transport equation is solved by the Monte Carlo method. The contribution of phonon, surface-roughness at both interfaces, and Coulomb scattering has been considered. The mobility decrease that appears experimentally in devices with a silicon film thickness under 20 nm is satisfactorily explained by an increase in phonon scattering as a consequence of the greater confinement of the electrons in the silicon film     

SOI MOSFET effective channel mobility

The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface. The effective channel mobility in fully-depleted n-channel SOI MOSFET's is shown to be independent of applied backgate bias when the modified E_eff definition is used. The effective channel mobility as a function of E_eff is also shown to be independent of film thickness for fully-depleted devices     

On the universality of inversion layer mobility in Si MOSFET's:Part I-effects of substrate impurity concentration

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10¹⁵ to 10¹⁸ cm^-3). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E_eff) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10¹⁸ cm ^-3. The E_eff dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO₂ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

埋氧层固定界面电荷对RESURF SOI功率器件击穿特性的影响

通过求解具有界面电荷边界条件的二维泊松方程，建立了埋氧层固定界面电荷Qf对RESURF SOI功率器件二维电场和电势分布影响的解析模型。解析结果与半导体器件模拟器MEDICI数值分析结果相吻合。在此基础上，分别研究了Qf对RESURF SOI功率器件横向和纵向击穿特性的影响规律。在横向，讨论了不同硅膜厚度、氧层厚度和漂移区长度情况下Qf对表面电场分布的影响；在纵向，通过分析硅膜内的场和势的分布，提出了临界埋氧层固定界面电荷密度的概念，这是导致器件发生失效的最低界面电荷密度。     

A model for hot-electron-induced MOSFET linear-current degradationbased on mobility reduction due to interface-state generation

A simple model for the hot-electron degradation of MOSFET linear-current drive is developed on the basis of the reduction of the inversion-layer mobility due to the generation of interface states. The model can explain the observed dependence of the device hot-electron lifetime on the effective channel length and oxide thickness by taking into account both the relative nonscalability of the localized damage region and the dependence of the linear-current degradation on the effective vertical electric field E_eff. The model is verified for deep-submicrometer non-LDD n-channel MOSFETs with L_eff=0.2-1.5 μm and T_ox=3.6-21.0 nm. From the correlation between linear-current and charge-pumping degradation, the scattering coefficient α, which relates the number of generated interface states to the corresponding amount of inversion-layer mobility reduction, can be extracted and its dependence on E_eff determined. Using this linear-current degradation model, existing hot-electron lifetime prediction models are modified to account explicitly for the effects of L_eff and T _ox     

Electron mobility behavior in extremely thin SOI MOSFET's

Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t_si region. The reasons for the mobility decrease have been examined from a device simulation and measurements     

The Corbino Pseudo-MOSFET on SOI: Measurements, Model, and Applications

We propose the combination of magnetoresistance (MR) and Pseudo-MOSFET ($ Psi$-MOSFET) measurements as an improved method for the characterization of silicon-on-insulator (SOI) materials. Measurements were performed on ultrathin SOI $Psi$ -MOSFETs with Corbino geometry by applying high magnetic field and substrate biasing. Several models and extraction methods are developed and compared for an accurate evaluation of electron mobility. In particular, the series resistance effect is removed by using appropriate corrections. The MR mobility can be determined at low or variable electric field. The MR mobility behavior is investigated as a function of effective electric field, temperature, and film thickness. The correlation between the MR mobility and effective mobility, determined in $Psi$-MOSFETs at zero magnetic field, enables a detailed analysis of the electron transport and scattering mechanisms in the silicon thin film.      

Influence of dielectric constant distribution in gate dielectrics on the degradation of electron mobility by remote Coulomb scattering in inversion layers

It has been reported that mobility in high-/spl kappa/ gate dielectric metal-insulator semiconductor field-effect transistors is lower than that in conventional metal-oxide semiconductor field-effect transistors and the reason for this degradation has been considered to be the fixed charge in dielectric films as well as remote phonon scattering. We investigated the influence of dielectric constant distribution in gate dielectrics on electron mobility determined by remote Coulomb scattering (/spl mu//sub RCS/) using numerical simulations and a physical model. It is shown that electron mobility in the inversion layer is strongly affected by the dielectric constant distribution in gate dielectrics. In the case of stacked-gate dielectrics of a high-/spl kappa/ film and an interfacial layer, mobility has a minimum as the dielectric constant of the interfacial layer increases while it increases virtually monotonically with dielectric constant of the high-/spl kappa/ film. These phenomena are explained, considering the electrical potential in the substrate induced by fixed charges in gate dielectrics using the Born approximation. Preferable dielectric constant distribution is presented in terms of the suppression of the remote Coulomb scattering.     

Buried-oxide charge trapping induced performance degradation infully-depleted ultra-thin SOI p-MOSFET's

The buried-oxide charge trapping induced performance degradation was studied in fully-depleted, ultra-thin SOI p-MOSFET's fabricated on SIMOX wafers. The trapped holes were introduced by X-ray irradiation, and the trapped electrons were introduced by hot hole impact ionization. Subthreshold slope and current drive degradations were observed due to hole-trapping in the buried oxide, via electrostatic coupling between the front and back interfaces. Simulation results showed much reduced performance degradation in SOI p-MOSFET's using thin buried oxides. A minimal interaction of front-channel hot-carrier and radiation effects on the buried oxide degradation, was observed in 0.3-μm channel length transistors