Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.     

Enhanced mobility PMOSFETs using tensile-strained Si1-yCy layers

We demonstrate for the first time that carbon incorporation in Si epitaxial layers may be an alternative method to deposit enhanced mobility tensile-strained Si MOSFET channel layers directly on a silicon substrate, thereby eliminating the need to deposit a thick relaxed SiGe buffer layer, from which dislocations and other defects can propagate to the channel region. The fabrication and electrical properties of PMOSFETs with Si_1-yC_y alloy channel layers are reported in this paper for the first time. It is found that small amounts of C in Si films can produce high quality epitaxial material. PMOSFETs fabricated on these layers demonstrate enhanced hole mobility over that of control Si     

Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies

We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.     

Dose-rate effects of p-channel metal oxide semiconductor field-effect transistors at various biasing conditions

The total-dose response and annealing effect of p-channel metal oxide semiconductor field-effect transistors (PMOSFETs) were investigated at various dose rates and biasing conditions.The results show that the shift of threshold voltage is more obvious when the dose rate is decreased.Under the various dose rates and biasing conditions,some have exhibited a time-dependent effect and others showed enhanced low-dose-rate sensitivity (ELDRS).Finally,using the subthreshold-separating method,the threshold-voltage shift is separated into shifts due to interface states and oxidetrapped charges,and the underlying mechanisms of the observed effects are discussed.It has been indicated that the ELDRS effect results from the different quantities of the interface states generated at high and low dose rates.     

不同偏置条件下PMOSFETs的剂量率效应研究

研究了不同剂量率、不同偏置条件下,PMOSFETs的辐照响应特性;并对高剂量率辐照后的器件进行了与低剂量率辐照等时的室温退火。结果表明,随着剂量率的降低,PMOSFETs阈值电压的漂移更加明显;不同偏置条件、不同剂量率范围内表现出TDE和ELDRS两种不同的剂量率效应。利用亚阈分离技术对影响阈值电压漂移的氧化物陷阱电荷和界面态进行了详细的机理分析,认为ELDRS效应的产生是由界面态密度的差异导致的。     

Electron and hole quantization and their impact on deep submicronsilicon p- and n-MOSFET characteristics

A first-principles approach to inversion layer quantization, valid for arbitrarily complex band structures, has been developed. This has allowed, for the first time, hole quantization and its effects on p-MOSFET device characteristics to be studied. In addition, electron quantization effects are revisited, improving on previous, simpler approaches. In particular, the impact of quantization on the threshold voltages and “effective” gate oxide thicknesses of p- and n-MOSFETs is investigated. A simple compact model is provided to quantitatively describe the threshold voltage shifts at 300 K as a function of the doping concentration and the oxide thickness. The significance of hole quantization for buried channel p-MOS structures is also studied. The results can be used to both identify and model these effects using popular device simulators     

Polysilicon quantization effects on the electrical properties of MOS transistors

The quantum-mechanical behavior of charge carriers at the polysilicon/oxide interface is investigated. It is shown that a dark space depleted of free carriers is created at the interface as a consequence of the abrupt potential energy barrier, which dominates the polysilicon capacitance and voltage drop in all regions of operation of modern MOS devices. Quantum-mechanical effects in polysilicon lead to a reduction in the gate capacitance in the same way as substrate quantization, and to a negative voltage shift, which is opposed to the positive shift caused by carrier quantization in the channel. Effects on the extraction of device physical parameters such as oxide thickness and polysilicon doping are also addressed.     

Channel length influenced contribution of hole and electron trapping effect to threshold voltage stability in organic field effect transistors

Effect of channel length on hysteresis and threshold voltage shift in copper phthalocyanine (CuPc) based organic field effect transistors was studied. Contrary to expectation, longer channel length devices exhibited minimum threshold voltage shift. Influence of channel length on the contribution of hole and electron trapping to threshold voltage stability was determined. Shortest channel length devices exhibited highest electron trapping effect while longest channel devices exhibited minimum hole as well as electron trapping. Lower hole trap effect for longer channel length devices was suggested to be due to reduced longitudinal field between source and drain electrodes while minimum electron trapping was attributed to suppression of drain current by increased hole trap centres.     

Numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor

We report on a numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor (GaAs FET) using proprietary simulation software. The substrate is assumed to contain shallow acceptors compensated by deep levels. The ratio between the densities of deep and shallow levels is considered to be one hundred, which is a typical value for semi-insulating substrates. Although several traps may be present in the substrate but only the most commonly observed ones are considered, namely hole traps related to Cu and Cr, and the familiar native electron trap EL2. The current–voltage characteristics of the GaAs FET are calculated in the absence as well as in the presence of the above mentioned traps. It was found that the hole traps are affected by the gate voltage while the electron trap is not. This effect on the response of hole traps is explained by the fact that the quasi-hole Fermi level in the substrate is dependent on the gate voltage. However, the electron quasi-Fermi level in the substrate is insensitive to the gate voltage and therefore electron traps are not perturbed.     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

Hole mobility enhancement and Si cap optimization in nanoscale strained Si1−xGex PMOSFETs

P-channel metal-oxide-semiconductor field-effect-transistors (PMOSFETs) with a Si_1−xGe_x/Si heterostructure channel were fabricated. Peak mobility enhancement of about 41% in Si_1−xGe_x channel PMOSFETs was observed compared to Si channel PMOSFETs. Drive current enhancement of about 17% was achieved for 70 nm channel length (L_G) Si_0.9Ge_0.1 PMOSFETs with SiO₂ gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects were achieved for the buried channel Si_1−xGe_x devices with L_G=70 nm, by Si cap optimization, compared to the Si channel devices. Drive current enhancement without significant short channel effects (SCE) and leakage current degradation was observed in this work.     

Charge trapping in ultrathin hafnium oxide

The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/.     

Modeling of the subthreshold characteristics of SOI MOSFETs withfloating body

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current     

隔离技术对SOI PMOSFET中空穴迁移率的影响

在SIMOX和Smart- cut SOI衬底上采用L OCOS和MESA隔离技术制备了部分耗尽PMOSFET,虽然L O-COS隔离器件的阈值电压较小,但其跨导和空穴迁移率明显小于MESA隔离器件.模拟表明,L OCOS场氧生长过程中,由于Si O2 体积膨胀,在硅膜中形成较大的压应力,从而降低了空穴的迁移率.     

Analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs for circuit simulation

An analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs is presented. A simple polynomial approximation is used to model the sheet carrier concentration (p/sub s//sup H/) in the two-dimensional hole gas at the Si/SiGe interface. The interdependence of p/sub s//sup H/ and the hole concentration at the Si/SiO/sub 2/ interface (p/sub s//sup S/) is taken into account in the model, which considers current flow at both the Si/SiGe and the Si/SiO/sub 2/ interfaces. This model is applicable to compressively strained SiGe buried-channel heterostructure PMOSFETs as well as tensile-strained surface-channel PMOSFETs. The model has been implemented in SABER, a circuit simulator. The results from the model show an excellent agreement with the experimental data.