High-performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology

We have developed high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content (25%) fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques without using SiGe buffer structures. The maximum enhancement of electron and hole mobilities of strained-SOI devices against the universal mobility amounts to 85 and 53%, respectively. On the other hand, we have also observed the reduction of carrier mobility in a thinner strained-Si layer or at higher vertical electric field conditions. For the first time, we have demonstrated a high-speed CMOS ring-oscillator using strained-SOI devices, and its improvement amounts to 63% at the supply voltage of 1.5 V, compared to control-SOI CMOS.     

High-performance subquarter-micrometer gate CMOS technology

A single phosphorous-doped poly(n⁺)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltages exceed 8 V. The transconductances of 0.22-μm-gate-length n and p MOSFETs are 450 and 330 mS/mm, respectively, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider utilizing nMOSFETs of 0.16-μm gate length and pMOSFETs of 0.22-μm gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V     

Digital isolation amplifier in silicon-on-sapphire CMOS

The design and fabrication results of a monolithic four-channel digital isolation amplifier in a 0.5 mum silicon-on-sapphire technology is reported. The isolation device is manufactured in a single die, taking advantage of the isolation properties of the sapphire substrate. The individual isolation channels can operate in excess of 40 Mbit/s using digital phase-shift-keying modulation. Modulation of the input signal is used to increase immunity to errors at low input data rates. The device can tolerate ground bounces of 1 V/mus and isolate more than 800 V     

Designing low-power digital CMOS

The increasing levels of circuit integration are leading to the implementation of highly sophisticated algorithms. Many of the commercial application areas have a requirement for portability, which leads to the need for low-power design. This paper considers the issues and design solutions for complex low-power digital CMOS IC design     

Low-voltage and low-power Ku-band CMOS LNA using capacitive feedback

Analog Integrated Circuits and Signal Processing - An ultra-wideband (12–18 GHz) low-noise amplifier (LNA) using a 65 nm CMOS technology is proposed, in which a...     

A translinear principle based low-power high-precision RMS-to-DC converter in CMOS technology

Analog Integrated Circuits and Signal Processing - In the present study, a low-power high-precision current-mode CMOS true root mean square (RMS)-to-DC converter is presented based on the...     

A short-channel CMOS/SOS technology in recrystallized 0.3-µm-thick silicon-on-sapphire films

CMOS/SOS devices and circuits were fabricated in 0.3-µm-thick epitaxial silicon-on-sapphire (SOS) films. Two solid-phase epitaxial recrystallization techniques double solid-phase epitaxy (DSPE) and solid-phase epitaxy and regrowth (SPEAR) reduced the total microtwin concentrations in the Si layers more than tenfold, while increasing electron and hole inversion-layer mobilities between 30 and 45 percent. Leakage currents were substantially reduced in all SPEAR devices and in n-channel DSPE transistors, with some increase observed for p-channel DSPE devices. Drive currents and subthreshold slopes also showed significant improvement in both n- and p-devices. Propagation delays below 75 ps were obtained for CMOS/SOS inverters with Loff= 0.5 µm. The application of DSPE and SPEAR techniques to 0.3-µm SOS films will extend the scaling of CMOS/SOS to circuits with VLSI complexity.     

A low-power CMOS analog multiplier

A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.     

High-performance devices for a 0.15-μm CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 μm and minimum channel length below 0.1 μm. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 μm, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF₂ implant were used. Maximum high V _DS threshold rolloff was 250 mV at effective channel length of 0.06 μm. For the minimum channel length of 0.1 μm, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively     

High-performance metal/silicide antifuse [for CMOS technology]

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Ω, which is a factor of 10 less than that of Si-based antifuses (poly/n⁺ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory     

A low-power CMOS time-to-digital converter

A time-to-digital converter, TDC, with 780 ps lsb and 10-μs input range has been integrated in a 1.2-μm CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5±0.5 V, and the operating temperature range is -40 to +60°C. Single-shot accuracy is 3 ns and accuracy after averaging is ±120 ps with input time intervals 5-500 ns. In the total input range of 10 μs, the final accuracy after averaging is ±200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm×2.5 mm     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

Accurate low-power CMOS autozeroed comparator

A low-power CMOS autozeroed comparator suitable for high-frequency A/D convertors is discussed. The use of a source follower in the autozeroed inverter stage allows the circuit to provide an optimum tradeoff between speed, gain and power dissipation. Relationships are given that relate the time response, both in the autozeroing and comparating phase, to the circuit parameters. An experimental prototype, fabricated with a 2 mu m CMOS process is also presented.<>     

High-performance and low-power conditional discharge flip-flop

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

High-performance CMOS current comparator

A new high-performance CMOS current comparator is proposed. By adding two inverters in the feedback loop of Traff's comparator, the proposed comparator exhibits significant speed improvement especially for low input currents. Simulated in a 0.18 mum CMOS technology, the comparator achieves a 0.6 ns delay for a 100 nA input current at 1.8 V supply, which is about eight times faster than Traff's comparator.     

A low-power CMOS analog vector quantizer

We present a parallel analog vector quantizer (VQ) in 2.0-μm double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16×16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic template storage measures 60×78 μm². The output code is produced by a 16-cell winner-take-all (WTA) output circuit of linear complexity which selects the winning template with constant power-decay product, independent of input levels and scale. Experimental results demonstrate 34 dB analog input dynamic range and 0.7 mW power dissipation at 3 μs cycle     

Rail-to-rail low-power high-slew-rate CMOS analogue buffer

A low-power rail-to-rail CMOS analogue buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting in suitability for applications with large capacitive loads. Simulated results are provided.