一种应用于TDC的低抖动延迟锁相环电路设计

本文采用双延迟线和防错锁控制结构,结合对电荷泵等关键模块版图对称性的匹配控制,设计了一种针对（Time-to-Digital Converter,TDC）应用的宽动态锁定范围、低静态相位误差延迟锁相环（Delay-Locked Loop,DLL）电路.基于TSMC 0.35μm CMOS工艺,完成了电路的仿真和流片验证.测试结果表明,DLL频率锁定范围为40MHz-200MHz;静态相位误差161ps@125MHz;在无噪声输入的理想时钟驱动下,200MHz频率点下的峰-峰值抖动最大为85.3ps,均方根抖动最大为9.44ps,可满足亚纳秒级时间分辨的TDC应用需求.     

扩频通信系统的伪码跟踪技术研究

同步系统是无线电导航系统中的关键部分。而伪码跟踪技术又是同步的关键技术。文中对延迟锁定环（DLL）系统理论进行深入研究,建立了延迟锁定环（DLL）的数学模型,通过仿真对伪码跟踪技术进行了定性的探讨,在仿真的基础上使用Insight公司的FPGA开发系统,用测试电路实测了伪码跟踪的性能。     

延迟锁相环控制模块的VLSI设计与实现

介绍了一种可用于DLL的控制模块,设计了控制模块的具体电路,并着重优化了控制算法,使其锁定速度快、支持的输入时钟信号频率范围大、延迟信号相位抖动小.采用SMIC 0.18 μm CMOS工艺库进行设计和实现.经仿真测试,电路工作范围可达到10 MHz～1 GHz,最大锁定周期为32个输入时钟周期,最大相位抖动小于28 ps.整个控制模块芯片面积为300 μm×350 μm.     

DSSS接收机中一种延迟锁定环的设计与实现

延迟锁定环（DLL）是扩频接收机中实现PN码捕获和跟踪的一个重要部分，本文介绍了一种基于farrow结构的内插滤波器的延迟锁定环，并进行了数字化实现。通过MATLAB仿真，表明这种延迟锁定环可以比较好的解决PN码同步问题，并FPGA上实现了该算法，使数字解调的硬件实现具有很好的移植性和灵活性。     

延迟锁定环(DLL)及其应用

DLL可以产生精确的延迟效果而不受环境和工艺条件的影响 ,因而常用来生成稳定的延迟或多相位的时钟信号。文中介绍了延迟锁相环的结构 ,设计了 CMOS工艺 DLL具体电路 ,着重分析了新型的伪差分结构延迟单元 ,它可使设计简单而且单位延迟时间的选择更加灵活。文中还对 DLL在高速以太网发送电路中的应用作了具体的设计和仿真 ,运用 DLL使发送数据的上升、下降时间精确地控制在 4ns± 1 ns的范围内     

用于频率综合器的延迟锁相环的设计

设计了一种宽频率锁定范围、倍频数可编程的延迟锁相环。它引入了条件振荡控制电路,使该电路在保持DLL一阶系统和低抖动性能优势的基础上吸收了PLL倍频数可编程的优点;同时,该电路结合了设置延迟初始值和采用新型鉴相器两种宽频技术,具有宽频率工作范围。该延迟锁相环用SMIC 0.18μm 1.8 V CMOS工艺实现,锁定范围为1.56~100 MHz,可供选择的倍频数为1~16,输出频率范围从20 MHz到100 MHz。在输入最小频率、最大倍频数下,仿真的功耗约为9 mW,抖动约为92 ps。     

基于防错锁控制结构的延迟锁相环设计

本文提出了一种防错锁控制结构,有效的解决了延迟锁相环教学和实践过程中出现的死锁定或谐波锁定等问题。基于0.18 μm CMOS工艺,完成了电路设计、版图设计以及后仿真。后仿真结果表明,在理想的时钟驱动下, 延迟锁相环在能准确锁定,确定性抖动为3.82 ps,自身随机性抖动为2 ps,可提供低抖动多相位的时钟。本文有助于学生理解掌握延迟锁相环精度和速度等设计要点,具有一定的教学指导意义。     

一种高频多相时钟发生电路的设计

给出了一种适用于分时采样结构A/D转换器的等间距8相时钟发生电路.介绍了延迟锁相环(DLL)的结构,给出了每一模块的具体模型并加以分析.在0.18 μm标准CMOS工艺和1.8V电源电压下,对电路进行了模拟仿真.仿真结果显示,在1.25 GHz的参考输入频率下,DLL输入每相延迟100 ps,锁定时间6.48 ns,总功耗为79 mW.     

一种低功耗倍频延迟锁相环设计

多相时钟是集成电路的关键模块之一,在模拟数字转换器(Analog-to-Digital Converter,ADC),或是时间数字转换器(Time-to-Digital Converter,TDC)等电路中有大量的应用.多相时钟通常由延迟锁相环(Delay-Locked Loop,DLL)与锁相环(Phase-Locked Loop,PLL)产生.然而传统DLL无法倍频,PLL会有抖动累积等问题.此外,DLL与PLL的功耗通常较大.针对这些问题,本文提出了一种低功耗防错锁倍频延迟锁相环(Multiplying Delay-Locked Loop,MDLL).该设计采用一种低功耗的电荷泵结构,以及能切换为压控振荡器的压控延迟线,使电路功能在DLL与PLL之间切换,在倍频的同时能够周期地消除抖动累积.同时加入了防错锁电路,以避免MDLL锁定在错误的频率.基于HHGrace 0.11μm COMS工艺进行了流片验证,芯片面积约为0.03 mm 2.测试结果表明,此电路能够将输入参考时钟倍频32倍输出,输出时钟频率范围为54.4 MHz-92.8 MHz,电路功耗为216μW–312μW.在输出时钟频率为80 MHz的情况下,均方根抖动为116.3ps(0.93%).     

一种用于高速流水线ADC的数字延迟锁相环电路

给出了一种应用于高速流水线A/D转换器的数字延迟锁相环电路.该电路的锁定过程采用顺序查找算法,设计了锁定检测窗口,用来判断延迟后的输出时钟信号是否满足锁定条件,根据检测结果即时调整延时大小,能有效避免误锁现象,准确完成延迟锁相功能.该数字延迟锁相环采用SMIC 0.18 μm 1.8 VCMOS工艺实现,频率范围为40～250 MHz.在输入最大频率下,仿真的锁定时间约为690 ns,抖动约为1.5 ps.     

Analysis of DLL Jitter due to Voltage-Controlled Delay Line

In this paper we analyze jitter in a delay-locked loop (DLL) due to uncertainties in the voltage-controlled delay line (VCDL). To obtain a closed-form equation for jitter in the DLL, time-domain equations of the DLL are used. The jitter at the intermediate stages of the VCDL and the jitter of a conventional delay cell are analyzed. The simulation results show that the jitter of the DLL due to mismatch of the delay cells is zero at the beginning and end of the VCDL and is highest at the middle of the VCDL. Also, a DLL is designed in TSMC 0.18 μm CMOS technology to show the accuracy of the proposed analytical method.     

An all-analog multiphase delay-locked loop using a replica delayline for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm²) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7]     

A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-$mu$m 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 $mu$m $times$ 381 $mu$m.      

A 250-MHz-2-GHz wide-range delay-locked loop

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.     

A wide-range delay-locked loop with a fixed latency of one clock cycle

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.     

Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers

A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and verified by the implementation of a delay cell in a 65-nm CMOS process.      

A high-resolution CMOS time-to-digital converter utilizing aVernier delay line

This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-μm digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding ±1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable     

可实现快速锁定的FPGA片内延时锁相环设计

延时锁相环（DLL）是一种基于数字电路实现的时钟管理技术。DLL可用以消除时钟偏斜,对输入时钟进行分频、倍频、移相等操作。文中介绍了FPGA芯片内DLL的结构和设计方案,在其基础上提出可实现快速锁定的延时锁相环OSDLL设计。在SMIC0．25μm工艺下,设计完成OSDLL测试芯片,其工作频率在20-200MHz,锁定时间相比传统架构有大幅降低。     

A dual-loop delay-locked loop using multiple voltage-controlleddelay lines

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-μm CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV     

A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration

A 3–8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters at 8 GHz are 11.44 and 6.67 ps before and after calibration, respectively. The power dissipation at 8 GHz is 18 mW for a supply voltage of 1.2 V, and the measured output duty cycle variation is less than 3%.