BiCMOS circuits for high speed current mode D/A converters

A new BiCMOS current cell and a BiCMOS current switch for high speed, self-calibrating, current-steering D/A converters are described. The BiCMOS current cell can be realized in a BiCMOS process or in a conventional CMOS process using a substrate PNP transistor, while the BiCMOS current switch is intended for implementation in a BiCMOS process. The performance of these circuits has been demonstrated in 0.8 μm BiCMOS and 1.2-μm CMOS technologies. A detailed noise analysis of the BiCMOS current cell indicates that noise during the calibration phase limits its relative accuracy to about 150 ppm. This is substantiated by measured results which show a relative matching of about 100-150 ppm, which is the equivalent of about 13 b performance. Measurement results also indicate that the absolute accuracy of the BiCMOS current cell is better than 0.5% over the designed current range, which is better than that of previously reported designs. Test results for the BiCMOS current switch indicate that a 10-90% switching time of 0.9 ns has been achieved. Furthermore, the switching time of the new BiCMOS switch is very insensitive to current level and input waveform compared to conventional CMOS switches. A 4-b D/A converter based on these components has been fabricated, and test results have demonstrated that it is functional. This DAC will be used as the internal DAC of a ΣΔ modulator for over-sampled video and digital radio applications     

一种偏置电流可调节的高效率2.4GHz锗硅功率放大器

基于IBM0.35μm SiGe BiCMOS工艺BiCMOS5PAe实现了一种偏置电流可调节的高效率2.4GHz锗硅功率放大器。该功率放大器采用两级单端结构和一种新型偏置电路,除射频扼流电感外,其它元件均片内集成。采用的新型偏置电路用于调节功率放大器的静态偏置电流,使功率放大器工作在高功率模式状态或低功率模式状态。在3.5V电源条件下,功率放大器在低功率模式下工作时,与工作在高功率模式下相比,其功率附加效率在输出0dBm时提高了56.7%,在输出20dBm时提高了19.2%。芯片的尺寸为1.32mm×1.37mm。     

低压高速大驱动电流BiCMOS模拟开关单元

从改善速度和电流驱动能力出发,设计了4种BiCMOS模拟开关电路。设计过程中在电路的关键部位配置有限的双极型晶体管(BJT),而在电路的主体部分则设置CMOS器件。推导出电路的传延时间估算式,优选了元器件参数,并采取提速和增大驱动电流的措施。实验结果表明,所设计的BiCMOS开关电路在低电源电压2.6V≤VDD≤4.0V的范围内,综合性能指标——延迟-功耗积DP比CMOS开关电路平均降低了36.52pJ,输出级BJT的驱动电流可达1.40mA以上,因而特别适用于低压、高速、大驱动电流的数字通信系统中。     

A Novel SiGe PIN Diode SPST Switch for Broadband T/R Module

A novel octagonal SiGe p-type intrinsic n-type (PIN) diode single pole single throw (SPST) switch is first implemented in a standard 0.18-mum SiGe BiCMOS technology. Distinctive radio frequency performance of monolithic silicon PIN diode switch is achieved for broadband applications with improvement of its geometry. Over the 2-16GHz frequency band, the PIN diode SPST switch exhibits an insertion loss of less than 1dB and isolation between 42dB to 19dB. An accurate small signal model of series PIN diode is also presented     

A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon–germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm² and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.     

A 2.4-GHz SiGe HBT power amplifier with bias current controlling circuit

A 2.4-GHz SiGe HBT power amplifier (PA) with a novel bias current controlling circuit has been realized in IBM 0.35-μm SiGe BiCMOS technology, BiCMOS5PAe. The bias circuit switches the quiescent current to make the PA operate in a high or low power mode. Under a single supply voltage of 3.5 V, the two-stage mode-switchable power amplifier provides a PAE improvement up to 56.7% and 19.2% at an output power of 0 and 20 dBm, respectively, with a reduced quiescent current in the low power mode as compared to only operating the PA in the high power mode. The die size is only 1.32 × 1.37 mm2.     

Increased current gain and suppression of peripheral base currentsin silicide self-aligned narrow-width polysilicon-emitter transistors ofan advanced BiCMOS technology

Silicidation of the emitter and base regions of the bipolar transistors of an advanced single-level polysilicon BiCMOS (bipolar complementary metal oxide semiconductor) technology is observed to result in an anomalously strong dependence of common-emitter current gain on emitter width. This effect is attributed to an increase in the peripheral component of the base current associated with the silicide extrinsic base at the periphery of the emitter. It is demonstrated that the current gain of silicide narrow-emitter transistors may be doubled by the introduction of a lightly doped extrinsic base region (LDEB) below the oxide-sidewall spacer. Further improvement by a factor of 2-3 may be achieved by increasing the width of the oxide-sidewall spacer     

An 8-b, 40 msamples/s switched-current-mode track-and-hold circuiton a BiCMOS sea-of-gates array

A fully differential track-and-hold circuit based on the switched-current processing has been integrated on a fully complementary 1.2 μm-6 GHz BiCMOS sea-of-gates array. It is based on a BiCMOS switched-current memory cell which uses MOS transistors to store the analog information and bipolar transistors to implement the switch. This improves the speed achievable and the distortion compared to a CMOS-only switched-current memory cell. A differential configuration is also presented which made it possible to improve performances such as the hold mode feedthrough (<-67 dB @ 10 MHz) or the pedestal error. The acquisition time for a full scale step is 22 ns, in order to reach the final value within 0.1%. It achieves 8-b precision at a sample-rate of 40 MHz under Nyquist condition, a full scale track-mode bandwidth of 150 MHz and a consumption of 80 mW for a surface of 0.44 mm²     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

Application of merged current switch logic for a built-in logicblock observer operating at 1 Gbit/s and 1.2 V supply

The authors show that merged current switch logic is an excellent candidate for enabling low supply voltages and maintaining an operating speed in the GHz range. The demonstration circuit fabricated in a 0.8 μm BiCMOS process operates at supply voltages as low as 1.2 V with a bit rate of 1 Gbit/s. The dynamic power consumption is 461 μW/gate     

A one-chip scalable 8*8 ATM switch LSI employing shared bufferarchitecture

The authors present a one-chip scalable 8×8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 μm BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated     

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit

A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder     

A single-power-supply 10-b video BiCMOS sample-and-hold IC

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2-μm BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW     

Merged CMOS/bipolar current switch logic (MCSL)

A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-bit BiCMOS full adder was measured. This is about five times faster than an optimized CMOS adder.<>     

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

This paper proposes a novel low-leakage BiCMOS deep-trench (DT) diode in a 0.18-/spl mu/m silicon germanium (SiGe) BiCMOS process. By means of the DT and an n/sup +/ buried layer in the SiGe BiCMOS process, a parasitic vertical p-n-p bipolar transistor with an open-base configuration is formed in the BiCMOS DT diode. Based on the two-dimensional (2-D) simulation and measured results, the BiCMOS DT diode indeed has the lowest substrate leakage current as compared to the conventional p/sup +//n-well diode even at high temperature conditions, which mainly results from the existence of the parasitic open-base bipolar transistor. Considering the applications of the diode string in electrostatic discharge (ESD) protection circuit designs, the BiCMOS DT diode string also provides a good ESD performance. Owing to the characteristics of the low leakage current and high ESD robustness, it is very convenient for circuit designers to use the BiCMOS DT diode string in their IC designs.     

An intelligent BiCMOS/DMOS quad 1-A high-side switch

A fully protected quad high-side DMOS switch has been realized using a BiCMOS/DMOS process. A bipolar multiplier cell calculates and limits instantaneous power dissipated by each 0.8-Ω DMOS power switch to 13 W. The integrated circuit shuts down to protect itself if a safe temperature or operating voltage is exceeded. A thermal warning is provided when the junction temperature rises to within 20°C of the shutdown temperature such that an orderly system turn-off occurs. A serial output data pin reports status information including channel on/off, open and shorted load faults, warning and shutdown temperatures, and an overvoltage condition. The circuit withstands a supply voltage of 60 V and operates from 6 to 32 V. The IC can be permanently connected to the power while drawing no DC current in the standby mode. The device fits into a 20-pin dual-in-line package having the die-attach paddle and the center four pins of the lead frame being a continuous strip of metal providing a low thermal resistance path from which to extract heat from the output switches     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W