A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.     

TWO APPROACHES TO THE DESIGN OF TIME-VARYING CASCADED FILTERS

Two approaches to the design of time-varying cascaded filters used in radar clutter rejection are presented. In the first approach, by fitting the cascaded filter to the noncascaded filter, the time-varying cascaded filter can be designed, which makes it possible that the time-varying cascaded filter behaves just like an optimum clutter filter. The second approach can be used to design the second-stage filter in a time-varying cascaded one by setting zeros in its equivalent overall frequency response. It has been shown that it is difficult to express the frequency response of the second-stage filter in the time-varying cascaded one, however, it is convenient to be involved in the overall response.     

Physical origins of input filter oscillations in current programmedconverters

Addition of an input filter to a current-programmed converter can cause the controller to oscillate. Two instability mechanisms can typically occur: (1) the current programmed controller effective current feedback loop may become unstable, or (2) the controller effective input voltage feedforward loop, which becomes a positive feedback loop when an input filter is added, may oscillate. Three design criteria for preventing oscillations are derived and interpreted. When all three criteria are well satisfied, then the output voltage regulation loop gain is unchanged. Hence, input filters of current programmed converters can be designed in essentially the same manner as for duty-ratio programmed converters. Results are summarized in tabular form for the basic buck, boost, and buck-boost converters. Experimental measurements for a buck converter with different input filters support the theoretical predictions     

时变级联滤波器的两种设计方法

本文针对雷达杂波抑制中常用的时变级联滤波器,提出了两种实用的设计方法。第一种方法通过时变级联滤波器与时变非级联滤波器的等效来设计时变级联滤波器。该方法可以使时变级联滤波器具有最佳杂波滤波器的效果。第二种方法通过对总的等效滤波器的设计来得到级联滤波器第二级的权系数。分析表明,时变级联滤波器第二级的频率响应很难写出,但可以通过总的等效频率响应来体现。     

Switched-capacitor filters

A novel technique for building active filters using switched-capacitor (SC) circuits is proposed. Principles of operation, methods of control, analysis, and design of a typical SC filter are presented. To assess its effectiveness, the technique is used to control input current harmonics in a phase-controlled converter. It is shown that a wide range of harmonics can be controlled using a single filter     

Input filter interactions in peak-current-mode-controlled buckconverter operating in CICM

Peak-current-mode (PCM) control is a widely used method to control switched-mode converters. Most often an input filter is necessary to meet electromagnetic interference requirements. The input filter can cause instability and degradation of input and output dynamics if not properly designed. The input filter design from the output dynamics viewpoint has been addressed in numerous papers, resulting in well-agreed results in the case of direct duty-ratio control. The same methods and criteria have also been applied to PCM control, but the results have turned out to be conflicting. This paper shows that the adverse effect of the input filter on the output performance of a peak-current-controlled buck converter in continuous inductor-current mode is insignificant. The input performance is, however, significantly affected, necessitating the use of proper damping. It is also shown that the instability is caused solely by the instability of the input filter under negative incremental resistance. The methods used are unified in nature, but the results obtained in this study cannot be generalized to be valid for types of converters other than a buck converter     

Optimal design of two-channel nonuniform-division FIR filter bankswith -1, 0, and +1 coefficients

This paper deals with the optimal design of two-channel nonuniform-division filter (NDF) banks whose linear-phase FIR analysis and synthesis filters have coefficients constrained to -1, 0, and +1 only. Utilizing an approximation scheme and a weighted least squares algorithm, we present a method to design a two-channel NDF bank with continuous coefficients under each of two design criteria, namely, least-squares reconstruction error and stopband response for analysis filters and equiripple reconstruction error and least-squares stopband response for analysis filters. It is shown that the optimal filter coefficients can be obtained by solving only linear equations. In conjunction with the proposed filter structure, a method is then presented to obtain the desired design result with filter coefficients constrained to -1, 0, and +1 only. The effectiveness of the proposed design technique is demonstrated by several simulation examples     

Boundary implications for frequency response of interval FIR andIIR filters

It is shown that vertex implication results in parameter space apply to interval trigonometric polynomials. Subsequently, it is shown that the frequency responses of both interval FIR and IIR filters are bounded by the frequency responses of certain extreme filters. The results apply directly in the evaluation of properties of designed filters, especially because it is more realistic to bound the filter coefficients from above and below instead of determining those with infinite precision because of finite arithmetic effects. Illustrative examples are provided to show how the extreme filters might be easily derived in any specific interval FIR or IIR filter design problem     

Continuous-time envelope-constrained filter design via DSP approach

In envelope-constrained (EC) filter design, the effect of input noise is minimised subject to the constraint that the filter's response to a specified signal fits into a prescribed envelope. The continuous-time version of this problem has been addressed using orthonormal analogue filters. The paper addresses the EC filter-design problem using a filter comprised of an A/D converter, a digital processor, a D/A converter and an analogue interpolation filter. Numerical results are presented for a number of design examples     

Adaptive Sliding-Mode Position Control for Piezo-Actuated Stage

The effect and design criteria of the input filter for buck converters with peak current-mode (PCM) control are researched using a novel system block diagram. With this diagram, a novel current loop transfer function is proposed to derive the design criteria that apply to designing the input filter. However, the input filter that is added to reduce electromagnetic interference will significantly change the dynamic property of the PCM-controlled buck converter. Therefore, the induced effect due to the input filter is examined. Finally, experimental results prove the accuracy of this deduction in both the circuit simulation and the circuit experiment.     

Low delay FIR filter banks: design and evaluation

The subject of this paper is the design of low and minimum delay, exact reconstruction analysis-synthesis systems based on filter banks. It presents a time domain approach to the problem of designing FIR filter banks with adjustable reconstruction delays. It is shown that using a time domain formulation for the analysis-synthesis systems, the system delay can be considered to be relatively independent of the length of the analysis and synthesis filters. After a summary of the time domain analysis and design framework, the design of low and minimum delay systems is considered in detail. Several design examples are provided in the paper to demonstrate the performance of the design algorithm     

New approaches to robust minimum variance filter design

This paper is concerned with the design of robust filters that ensure minimum filtering error variance bounds for discrete-time systems with parametric uncertainty residing in a polytope. Two efficient methods for robust Kalman filter design are introduced. The first utilizes a recently introduced relaxation of the quadratic stability requirement of the stationary filter design. The second applies the new method of recursively solving a semidefinite program (SDP) subject to linear matrix inequalities (LMIs) constraints to obtain a robust finite horizon time-varying filter. The proposed design techniques are compared with other existing methods. It is shown, via two examples, that the results obtained by the new methods outperform all of the other designs     

Dynamics analysis and controller synthesis forzero-voltage-transition PWM power converters

A small signal model for zero-voltage-transition pulse width modulation (ZVT-PWM) buck converters is proposed in this paper. It shows that the ZVT-PWM buck converter exhibits better dynamical behavior than the conventional PWM buck converter. Based on the derived model consisting of line voltage disturbances and load variations, μ-synthesis is applied for a robust controller design to achieve performance requirement. In addition, a classical controller and a sliding mode controller with modified integral variable structure are also designed for performance comparisons. Finally, simulation and experimental results are presented to verify the requirement for robust performance of ZVT-PWM converters     

Input filter design for power factor correction circuits

The issues involved in the design of power factor correction circuit input filters are significantly different from those involved in the design of input filters for DC-DC power converters. In many cases, the EMI and power factor requirements are impossible to meet using the existing filtering technology. This paper proposes the use of high-order elliptic filters to achieve the required EMI attenuation and power factor. The new input filter technology provides a significant filter size reduction over the standard filter designs, minimizes the filter-power converter interaction, and maintains a good converter power factor. New active and passive filter damping methods that guarantee optimal filter pole damping, while virtually eliminating damping resistor power dissipation, are proposed. The filter design procedure that makes possible a simple and fast design of filters with an arbitrary number of stages is also presented     

A Novel Control Technique for a Switched-Capacitor-Converter-Based Hybrid Electric Vehicle Energy Storage System

This paper presents the analysis and novel controller design for a hybrid switched-capacitor bidirectional dc/dc converter. Features of voltage step-down, step-up, and bidirectional power flow are integrated into a single circuit. The novel control strategy enables simpler dynamics compared to a standard buck converter with an input filter, good regulation capability, low electromagnetic interference, lower source current ripple, ease of control, and continuous input current waveform in both modes of operation (buck and boost modes).      

A new control algorithm for three-phase PWM buck rectifier withinput displacement factor compensation

A new control algorithm for the three-phase buck rectifier with an input filter is developed. The algorithm employs a separate control loop for compensation of the input current displacement factor in steady-state, in addition to the standard output voltage regulation loop. The algorithm allows separate design of the input filter and of closed-loop output voltage control. The design procedure is explained and illustrated with an example. The algorithm is verified experimentally on a 1 kW, 100 kHz, three-phase isolated buck converter     

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.     

Design and evaluation of Feedforward Active ripple filters

An active ripple filter is an electronic circuit that cancels or suppresses the ripple current and electromagnetic interference generated by the power stage of a power converter, thus reducing the passive filtration requirements. This paper explores the design of feedforward active ripple filters for current ripple cancellation, including the design tradeoffs, advantages, and limitations of different implementation methods. The design and performance of an active filter using a novel Rogowski-coil current sensor is discussed in detail. Experimental results from a prototype converter system using this approach are presented, and quantitative comparisons are made between a hybrid passive/active filter and a purely passive filter. It is demonstrated that substantial improvements in filter mass and converter transient performance are achievable using this active ripple filtering method.     

Design of IIR orthogonal wavelet filter banks using lifting scheme

The lifting scheme is well known to be an efficient tool for constructing second generation wavelets and is often used to design a class of biorthogonal wavelet filter banks. For its efficiency, the lifting implementation has been adopted in the international standard JPEG2000. It is known that the orthogonality of wavelets is an important property for many applications. This paper presents how to implement a class of infinite-impulse-response (IIR) orthogonal wavelet filter banks by using the lifting scheme with two lifting steps. It is shown that a class of IIR orthogonal wavelet filter banks can be realized by using allpass filters in the lifting steps. Then, the design of the proposed IIR orthogonal wavelet filter banks is discussed. The designed IIR orthogonal wavelet filter banks have approximately linear phase responses. Finally, the proposed IIR orthogonal wavelet filter banks are applied to the image compression, and then the coding performance of the proposed IIR filter banks is evaluated and compared with the conventional wavelet transforms.     

FIR, Allpass, and IIR Variable Fractional Delay Digital Filter Design

This paper presents two-step design methodologies and performance analyses of finite-impulse response (FIR), allpass, and infinite-impulse response (IIR) variable fractional delay (VFD) digital filters. In the first step, a set of fractional delay (FD) filters are designed. In the second step, these FD filter coefficients are approximated by polynomial functions of FD. The FIR FD filter design problem is formulated in the peak-constrained weighted least-squares (PCWLS) sense and solved by the projected least-squares (PLS) algorithm. For the allpass and IIR FD filters, the design problem is nonconvex and a global solution is difficult to obtain. The allpass FD filters are directly designed as a linearly constrained quadratic programming problem and solved using the PLS algorithm. For IIR FD filters, the fixed denominator is obtained by model reduction of a time-domain average FIR filter. The remaining numerators of the IIR FD filters are designed by solving linear equations derived from the orthogonality principle. Analyses on the relative performances indicate that the IIR VFD filter with a low-order fixed denominator offers a combination of the following desirable properties including small number of denominator coefficients, lowest group delay, easily achievable stable design, avoidance of transients due to nonvariable denominator coefficients, and good overall magnitude and group delay performances especially for high passband cutoff frequency ( ges 0.9pi) . Filter examples covering three adjacent ranges of wideband cutoff frequencies [0.95, 0.925, 0.9], [0.875, 0.85, 0.825], and [0.8, 0.775, 0.75] are given to illustrate the design methodologies and the relative performances of the proposed methods.