Electrical properties of metal–HfO2–silicon system measured from metal–insulator–semiconductor capacitors and metal–insulator–semiconductor field–effect transistors using HfO2 gate dielectric

Metal–insulator–semiconductor (MIS) capacitors and metal–insulator–semiconductor field effect transistors (MISFETs) incorporating HfO₂ gate dielectrics were fabricated using RF magnetron sputtering. In this work, the essential structures and electrical properties of HfO₂ thin film were examined. The leakage current measured from MIS capacitors depends on the sputtering gas mixture and the annealing temperature. The best condition to achieve the lowest leakage current is to perform the annealing at 500 °C with a mixture of 50% N₂ and 50% O₂ gas ratio. Aluminum is used as the top electrode. The Al/HfO₂ and the HfO₂/Si barrier heights extracted from Schottky emission are 1.02 eV and 0.94 eV, respectively. An Al/HfO₂/Si energy band diagram is proposed based on these results.     

Transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with Al2O3 of different thickness

The Al₂O₃ as a gate oxide and passivation was used to study the transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs). Performance of the devices with Al₂O₃ of different thickness between 4 and 14 nm prepared by metal–organic chemical vapor deposition (MOCVD) and with 4 nm thick Al₂O₃ prepared by Al sputtering and oxidation was investigated. All MOS-devices yielded higher transconductance than their HFET counterparts, i.e. the transconductance/capacitance expected proportionality assuming the same carrier velocity was not fulfilled. A different electric field near/below the gate contact due to a reduction of traps is responsible for the carrier velocity enhancement in the channel of the MOSHFET. The trap reduction depends on the oxide used, as follows from the capacitance vs frequency dispersion for devices investigated. It is qualitatively in a good agreement with the different velocity enhancement evaluated, and devices with thinner oxide show higher traps reduction as well as higher transconductance enhancement. It is also shown that obtained conclusions can be applied well on performance of SiO₂/AlGaN/GaN MOSHFETs.     

Optimization and performance of Al2O3/GaN metal–oxide–semiconductor structures

We investigate electrical properties of Ni/Al₂O₃/GaN metal–oxide–semiconductor (MOS) structures having different pre-treatment of GaN surface by O₂, Ar and NH₃, combined with various temperature of annealing. MOS and reference Ni/GaN Schottky contact are characterized using current–voltage and capacitance–voltage methods. MOS structures compared with the Schottky contact ones show leakage current reduction for all types of processing, from 3 to 5 orders of magnitude in reverse direct. We observed substantial influence of the pre-treatment on electrical parameters of MOS structures.     

Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

For PMOS (p-channel metal–oxide–semiconductor) transistors isolated by shallow trench isolation (STI) technology, reverse narrow width effect (RNWE) was observed for large gate lengths such that the magnitude of the threshold voltage becomes smaller when the channel width decreases. However, PMOS transistors with small gate lengths show up a strong anomalous narrow width effect such that the magnitude of the threshold voltage becomes larger when the channel width decreases. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic transient enhanced diffusion (TED) due to Si interstitials generated by the deep boron source/drain (S/D) implant towards the gate/STI edge.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

First investigation of metal–insulator–metal (MIM) capacitor using Pr2O3 dielectrics

Metal–insulator–metal (MIM) capacitors with Pr₂O₃ as high-k material have been investigated for the first time. We varied the thickness of the Pr₂O₃ layers as well as the bottom electrode material. The layers are characterised using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), transmission electron microscopy (TEM) and secondary ion mass spectroscopy (SIMS). Preliminary information on the interaction of water with the films was obtained from XPS and ab initio pseudopotential calculations. The electrical characterisation shows that Pr₂O₃ MIM capacitors can provide higher capacitance densities than Si₃N₄ MIM capacitors while still maintaining comparable voltage coefficients of capacitance. The Pr₂O₃ dielectric material seems to be suitable for use in silicon RF applications.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

Electrical and structural characterization of PLD grown CeO2–HfO2 laminated high-k gate dielectrics

The electrical and physical properties of CeO₂–HfO₂ nanolaminates deposited by pulsed laser deposition (PLD) are investigated. The properties of the nanolaminates are compared with binary CeO₂ and HfO₂ thin films. Layers were deposited using CeO₂ and HfO₂ targets at substrate temperatures between 220 and 620 °C in 10 Pa Ar+H₂ or O₂. In situ post deposition anneal (PDA) was achieved by controlled cooling down to room temperature with . Nanolaminates starting with CeO₂ show lower EOT and leakage compared to layers starting with HfO₂. TEM and XRD analyses showed thickness-dependent crystallinity of the layers, varying from amorphous to highly oriented polycrystalline phase.C–V and I–V measurements were done on the capacitors. Lowest fixed-charge density was found for the nanolaminates deposited at 520 °C. The k values of the nanolaminates extracted by the EOT-physical thickness plots were found to be 141, 48 and 22, for deposition temperatures 420, 520 and 620 °C, respectively. Higher k value for lower deposition temperatures is explained by the thickness dependent morphology of the layers. An with was found for binary HfO₂ layer with 4 nm physical thickness. Lowest leakage current density was for a 4 nm laminate deposited at 420 °C and with a cooling rate of 2 °C/min during PDA.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructure

Ultrathin HfO₂ gate dielectrics have been deposited on strain-compensated Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. X-ray diffraction spectra show the films to be polycrystalline having both monoclinic and tetragonal phases. The formation of an interfacial layer has been observed by high-resolution transmission electron microscopy. Secondary ion mass spectroscopy and Auger electron spectroscopy analyses show the formation of an amorphous Hf-silicate interfacial layer between the deposited oxide and SiGeC films. The average concentration of Ge at the interfacial layer is found to be 2–3 at%. The leakage current density of HfO₂ gate dielectrics is found to be several orders of magnitude lower than that reported for thermal SiO₂ with the same equivalent thickness.     

A high performance MIM capacitor using HfO2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO₂ high-κ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (~200°C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO₂ MIM capacitor can provide a higher capacitance density than Si₃N₄ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2×10^-9 A/cm² at 3 V is achieved. All of these make the HfO ₂ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications     

Controllable carrier density of pentacene field-effect transistors using polyacrylates as gate dielectrics

We have studied the effect of the chemical structure of dielectrics by evaporating pentacene onto a series of polyacrylates: poly(methylmethacrylate), poly(4-methoxyphenylacrylate), poly(phenylacrylate), and poly(2,2,2-trifluoroethyl methacrylate) in organic thin-film transistors (OTFTs). In top-contact OTFTs, the polyacrylates had a significant effect on field-effect mobilities ranging 0.093 ∼ 0.195 cm² V⁻¹ s⁻¹. This variation neither correlated with the polymer surface morphology nor the observed pentacene crystallite size. This result implies that the PTFMA device generates the local electric field that accumulates holes and significantly shifts the threshold voltage and the turn-on voltage to −8.62 V and 3.5 V, respectively, in comparison with those of PMMA devices.     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Reliability of gate dielectrics and metal–insulator–metal capacitors

In this review paper reliability characterisation methods of SiO₂ as gate dielectric and metal–insulator–metal capacitors with various dielectrics are discussed. It includes the test structure design, the stress and measurement sequences, the raw data analysis and the extrapolation models of measured time to breakdown to lifetimes at operating conditions and targeted product failure rates. For each topic various references are given where further details are described. Especially pitfalls of approaches and problem areas are highlighted.     

Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO₂) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO₂ physical thicknesses. However, it is more prominent (2 orders of magnitudes) for 2.5 nm HfO₂ film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO₂ film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO₂ gate dielectric layer compared to the 2.5 nm HfO₂ layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.     

Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs

In this paper, the threshold voltage instability characteristics of HfO₂ high-k dielectric are discussed. The results from various stress bias conditions including DC and AC with variations of frequency, duty cycle, and polarity provide additional insights into the intrinsic behavior and the trapping dynamics of high-k materials. A reduced threshold voltage shift was observed at higher frequency and lower duty cycle under AC positive unipolar stress compared to DC stress. Similarly, the degradation of maximum transconductance was also reduced with AC stress. However, subthreshold swing changes were found to be negligible and fairly independent of stress frequencies and duty cycles under AC positive unipolar stress.When different polarity of stress, such as positive, negative, and bipolar stress was applied, it was observed that frequency and duty cycle dependencies were still valid in all three conditions. In contrast to positive stress, negative stress showed a decrease in the threshold voltage shift. Bipolar stress resulted in the highest threshold voltage instability, but the degradation in transconductance and subthreshold swing was actually smaller than those in negative unipolar stress. The bulk trap of HfO₂ dielectric, which is proportional to its physical thickness, is believed to be the primary factor for threshold voltage shift. AC unipolar operation would allow a higher 10-year lifetime operating voltage than the DC condition. In addition to experimental results, a plausible mechanism has been proposed.     

Thickness limitations of SiO2 gate dielectrics for MOSULSI

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si₃N ₄ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.