一种用于非致冷红外焦平面读出电路的带隙基准源

设计了一种用于新型非致冷红外焦平面阵列读出电路的低温漂低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术.通过改进带隙基准电路中的带隙负载结构及基准核心电路,可以分别对基准电压和基准电流进行温度补偿.在0.5μm CMOS N阱工艺条件下,采用Spectre软件进行了模拟验证.仿真结果表明,在3.3 V条...     

基于新型非制冷IRFPA读出电路的带隙基准源

设计了一种用于新型非制冷IRFPA读出电路的低温漂的低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术,通过改进带隙基准电路中的带隙负载结构以及基准核心电路,基准电压和基准电流可以分别进行温度补偿.在0.5 μm CMOS N阱工艺条件下,采用spectre进行模拟验证.仿真结果表明,在3.3 V条件下,...     

带2阶补偿的CMOS带隙基准电压源

基于CSMC 0.5μm CMOS工艺,设计了一种具有低温度系数、带2阶补偿的带隙基准电压源.在传统放大器反馈结构带隙基准源的基础上,利用MOS器件的“饱和电流与过驱动电压成平方关系”产生2阶补偿量,对传统的带隙基准进行高阶补偿.具有电路实现简单,容易添加到传统带隙基准电路的优点.仿真结果表明,设计的基准电压源在5V电源电压下功耗为860 μW,最低工作电压为1.24 V,在-50℃～125℃的温度范围内获得了1.42×10-5/℃的温度系数,低频时的电源抑制比达到-86.3 dB.     

一种新型CMOS带隙基准电压源

传统带隙基准源电路采用PNP型三极管来产生ΔVbe,此结构使运放输入失调电压直接影响输出电压的精度。文章在对传统CMOS带隙电压基准源电路原理的分析基础上,提出了一种综合了一阶温度补偿和双极型带隙基准电路结构优点的高性能带隙基准电压源。采用NPN型三极管产生ΔVbe,消除了运放失调电压影响。该电路结构简洁,电源抑制比高。整个电路采用SMIC 0.18μmCMOS工艺实现。通过Cadence模拟软件进行仿真,带隙基准的输出电压为1.24V,在-40℃~120℃温度范围内其温度系数为30×10-6/℃,电源抑制比(PSRR)为-88 dB,电压拉偏特性为31.2×10-6/V。     

基于温度补偿的无运放低压带隙基准源设计

设计了一种带温度补偿的无运放低压带隙基准电路。提出了同时产生带隙基准电压源和基准电流源的技术,通过改进带隙基准电路中的带隙负载结构以及基准核心电路,基准电压和基准电流可以分别进行温度补偿。在0.5μmCMOS N阱工艺条件下,采用spectre进行模拟验证。仿真结果表明,在3.3V条件下,在-20～100℃范围内,带隙基准电压源和基准电流源的温度系数分别为35.6ppm/℃和37.8ppm/℃,直流时的电源抑制比为-68dB,基准源电路的供电电压范围为2.2～4.5V。     

一种输出可调CMOS带隙基准电压源的设计

传统设计中平衡温度时的带隙基准电压值是与工艺相关联的定值.主要基于通用的带隙技术讨论在CMOS工艺中基准产生的设计,在对基准产生原理与传统电路结构分析的基础上,设计出一种高PSRR输出可调带隙基准电压源.电路综合温度补偿、电流反馈和电阻分压技术,采用CSMC 0.5 tim CMOS混合信号工艺实现,并用Cadence的Spectre进行了仿真优化.仿真结果表明,带隙基准电压源在-15～80℃范围内输出为603.5 mV时的温度系数为6.84 × 10-6/℃,在1.8～5 V电路均可正常工作.流片后的测试结果验证了该方法的可行性,基准电压中心值可宽范围调整,各项性能参数满足设计要求.     

一种低温漂的无运放带隙基准电压源

针对传统无运放带隙基准电压源温度特性差的问题,设计了一种低温漂的无运放带隙基准电压源电路。设计中通过电流镜以及环路反馈的方法来代替传统运放对电路进行钳位,避免了运放输入失调电压对带隙基准电压精度的影响。同时基于华虹0.35μm BCD工艺,利用工艺库中温度系数不同的电阻来产生与温度相关的非线性项,从而对三极管负温度系数电压中的高阶非线性项进行补偿,实现了无运放带隙基准的低温漂特性。通过Cadence Spectre对电路进行仿真,仿真结果表明：在-55～125℃温度范围内,输入电压为5.5 V时,带隙基准电压的温漂系数为1.949×10^-6/℃;在10 kHz时,电源抑制比达到71.5 dB,在1 MHz时,电源抑制比达到46.3 dB。     

一种高精度带隙基准电压源电路设计

针对传统CMOS带隙电压基准源电路电源电压较高,基准电压输出范围有限等问题,通过增加启动电路,并采用共源共栅结构的PTAT电流产生电路,设计了一种高精度、低温漂、与电源无关的具有稳定电压输出特性的带隙电压源.基于0.5μm高压BiCMOS工艺对电路进行了仿真,结果表明,在-40℃～85℃范围内,该带隙基准电路的温度系数为7ppm/℃,室温下的带隙基准电压为1.215 V.     

低功耗CMOS带隙基准电压源设计

从带隙基准原理出发,通过对传统的带隙基准电路中的反馈环路进行了改进,设计了一种带启动电路的带隙基准电压源。带隙基准电压源电路具有结构简单、功耗低、电压抑制比高以及温度系数低等特点。采用TSMC 0.13μm工艺对电路进行流片,管芯面积为100μm×94μm。测试结果显示,电源电压1V时,在-30~120℃范围内温度系数为6.6×10-6/℃,功耗仅1.8μW;电源电压从0.76V变化到2V,输出电压偏差仅1.52mV,电源抑制比达58dB。     

一种10-ppm/~oC低压CMOS带隙电压基准源设计

在对传统CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈和电阻二次分压技术,提出了一种10-ppm/oC低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路的设计,放大器的输出用于产生自身的电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC 0.35mm CMOS工艺实现,采用Hspice进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

一种针对电容阵列的低功耗充放电方法——动态基准电平斜波充放电法

论述了一种用于主动阵列显示(如硅基液晶)的电容阵列充放电电路的降低功耗的方法,我们称之为动态基准电平斜波充放电法。这种方法利用一行电容上电平的分布特性,将一行的电容连通相互充放电,达到静电平衡,得到行平均电容。以行平均电容为基准电平,对输入信号高于行平均电平的像素进行充电,而对输入信号低于行平均电平的像素进行放电,使之达到输入信号的电平。经过计算,这种方法与一般的斜波充放电方法相比可以降低70%以上的电容充放电损耗。在头盔显示器中,由于对功耗有严格的限制,因此在头盔系统的硅基液晶显示器中采用本文所讨论的驱动方法,对于降低功耗、提高系统集成度具有重要意义。     

基于LDO稳压器的带隙基准电压源的设计

基准模块是LDO线性稳压器的核心部分,它是影响稳压器精度的关键因素之一。本文针对LDO线性稳压器对基准模块一方面有较高的精度要求,另一方面又有较低静态电流要求的矛盾设计了一款简单实用的电压基准电路。仿真结果表明该电路在-40~140℃的温度系数为7.7′10-6℃,低频时的电源抑制比可达-76dB,基准源电路的供电电压范围为2~4.5V。     

一种高电源抑制比曲率补偿带隙基准电压源

在对传统典型CMOS带隙电压基准源电路分析基础上提出了一种高精度、高电源抑制带隙电压基准源。采用二阶曲率补偿技术,电路采用预电压调整电路,为基准电路提供稳定的电源,提高了电源抑制比,在提高精度的同时兼顾了电源抑制比,整个电路采用了CSMC0.5μm标准CMOS工艺实现,采用spectre进行进行仿真,仿真结果显示当温度为-40℃~80℃,输出基准电压变化小于1mV,温度系数为3.29×10-6℃,低频时(1kHz)的电源抑制比达到75dB,基准电路在高于3.3V电源电压下可以稳定工作,具有较好的性能。     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine

Multi-supply voltage (MSV) technique is one of the efficient ways to reduce power consumption. However, MSV makes the physical design much more complicated. Especially, the randomized algorithm consumes much time as the size of the problem increases and the constraint of rectangular shaped voltage island limits better solutions in terms of power. In this paper, a nonrectangular shaped voltage island (NSVI) aware floorplanning is proposed with nonrandomized searching engine for efficient floorplanning. With a generalized slicing tree, a hypergraph is generated according to the cores' legal voltage levels, which is favorable to cluster cores working under the same voltage level together so that the called NSVIs can be generated easily. The proposed approach can deal with the fixed-outline floorplanning and perform well under different aspect ratios. Experimental results on GSRC benchmark suites indicate that the proposed method can obtain better solutions with less CPU time than published methods.     

基于干涉条纹相关性测量PZT相移特性的方法

闭环压电陶瓷(PZT)具有良好的线性特征,能实现纳米级分辨率,在微位移过程中响应快,精度高,广泛用于光学测量领域。在干涉测量中,利用PZT控制反射镜的移动,引入可控相移,需要知道PZT的电压相移特性。提出了基于干涉条纹图样的相关性测量PZT电压相移特性的方法,利用CMOS数字摄像机采集干涉条纹图样,以零电压对应的图样为基准图,做归一化相关系数运算,最后得到PZT电压相移特性曲线,满足了干涉测量相移可控的要求。     

峰值电流控制开关电源的反馈补偿问题研究

针对电流控制模式降压型开关电源芯片,探讨了输入电压的不同以及工作温度的差异造成对输出带负载能力和峰值电流的影响。在电流反馈回路的斜坡补偿模块中,加入随输入电压线性变化的基准电流源,以补偿不同输入电压对采样与斜坡补偿峰值电压造成的差异。此外,对反馈环中的比例电阻采用不同的工艺制作,通过电阻的温度系数补偿由采样电阻随温度变化所造成的采样电压的变化,减小温度对电路的带负载能力和峰值电流的影响。改进后,在相同环境温度下,4．7V到30V输入时,输出最大负载电流差异由2A降为0．5A。电阻改进后,从27℃到150℃,输出最大负载电流几乎不变。     

一种降低电路泄漏功耗的多阈值电压方法

目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。     

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of $V_{rm DD}$ and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.      

Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits

Reduction in leakage power consumption is one of the important issues in the field of VLSI. Numerous techniques have been proposed by several researchers, based on threshold voltage variations and gate modifications. In this paper, a novel pass transistor-based pull-up/pull-down insertion technique is proposed to minimize standby leakage. Experimental results on various ISCAS’89 benchmark circuits show that proposed technique has an improvement up to 20, 36 and 33 % on average in leakage reduction, delay improvement and area savings respectively, compared to the transmission gate-based technique. All benchmark circuits are simulated using H-spice Tool with an 180-nm standard cell library based on BSIM3 transistor model. Finally, the efficacy of the proposed approach in improving various metrics has been compared with present state-of-art methods.