基于PXI总线的航空串行总线专用通讯模块研制

ARINC429在航空航天等领域应用广泛,RS 232是常用的计算机与外部设备接口。作为某军事领域电子系统测试平台的一部分,设计了基于PXI总线的ARINC429和RS 232的专用通讯模块。以DSP和FPGA联合作为控制器,实现通讯模块的PXI接口,基于专用的协议芯片DEI1016实现ARINC429通讯,由FPGA为协议芯片提供时序和数据的缓存FIFO,并在FPGA中集成了RS 232协议编解码。测试表明,该通讯模块能实时可靠灵活地收发数据,实现对被测电子系统多路ARINC429和RS 232总线的测试。     

CRC5/16编码校验模块的FPGA一体化设计

在数字通信领域,为保证数据的正确传输,数据校验是必不可少的,而循环冗余校验(CyclicRedundancy Check,简称CRC)在其中得到广泛的应用。该文首先对CRC5/16校验的基本原理作了简要的介绍,然后对CRC5/16编码校验的具体电路及其实现步骤进行了详尽的阐述。在分析它们实现电路的基础上,提出了将CRC5/16的编码校验放在一个模块中实现的方法,这样不仅节省了硬件资源,而且系统的模块化设计也有利于模块的重复利用与移植。最后给出了在FPGA中的具体实现方法,并利用软件工具及硬件电路对该设计进行了较为全面的仿真验证。     

CRC算法在以太网数据帧中的应用及其硬件实现

文章介绍了CRC校验算法的原理,在串行CRC实现的基础上,对电路结构提出了改进,提出了CRC的并行计算,并基于Verilog HDL语言以CRC8为例说明了硬件电路实现方法。CRC校验广泛应用于数据通信、数据存储领域,结合IEEE802．3标准,说明了CRC算法在以太网帧FCS字段中的应用,并给出了CRC32_D16仿真结果。     

高速ATM中CRC算法与信元定界的FPGA实现

在通信领域循环冗余码CRC得到了广泛的应用。为解决高速ATM中信头误码差错控制和信元定界问题,通过对循环冗余校验原理的分析,采用递推的方法得出了一种高效的CRC算法。该算法能检测到多个bit错误,并能纠正单bit的错误。相对于一般的按位串行计算或者查表并行计算的方法,这种算法运算速度快且不需要额外的空间存储余数表,提高了高速链路上数据吞吐率。数据之间逻辑关系简单,十分便于采用FPGA实现。     

基于FPGA的高速同步HDLC通信控制器设计

高级数据链路控制HDLC协议是一种面向比特的链路层协议,具有同步传输数据、冗余度低等特点,是在通信领域中应用最广泛的链路层协议之一.提出实现HDLC通信协议的主要模块-CRC校验模块及'0'比特插入模块的FPGA实现方法.CRC校验模块采用状态机设计方法,而'0'比特插入模块是利用FIFO实现,为HDLC通信控制器的设计提供新的思路.该方法已在Spartan3s400开发板上实现,并能正确传输.     

一种用于高速数据采集的SDRAM控制器

同步动态随机存储器(SDRAM)在数据存储领域得到广泛的应用。针对一项基于PCI总线的高速数据采集系统提出了一种基于FPGA的SDRAM控制器的实现方法,FPGA中采用模块化设计方法。详细介绍了SDRAM控制器的组成结构和各模块功能,重点解决了SDRAM的刷新控制和空满检测问题,并对其进行了仿真验证,给出了全页读写模式下SDRAM的仿真时序图。仿真结果表明,SDRAM控制器实现了对SDRAM的读写操作,满足器件时序要求,完成了高速数据的大容量存储。     

循环冗余校验在数据采集系统中的应用

在激光光幕坐标靶的测试中,采用FPGA作为坐标数的数据采集和存储装置,为了克服其占用资源多、扩展性不强等特点,采用FPGA处理I/O数据,并通过并行算法的CRC校验与主控FPGA交换I/O信息的方法实现数据的存储。为了保证并行I/O数据传输的可靠性,用Verilog实现了并行算法CRC-32校验编码,给出了正确的仿真结果。在实际应用中,该校验器速度快,占用资源少,该方法实现了对数据的有效传输,具有I/O扩展的高度灵活性,为大面积坐标靶的实现提供可靠的理论基础。     

基于FPGA实现CRC校验功能的通用异步串口通信

UART作为RS-232协议的控制接口得到了广泛的应用,为实现准确的数据串口通信,在分析CRC生成算法的基础上,提出了一种简单、实用的UART设计与实现方案。该方案在串口通信中采用CRC-5校验,基于FPGA采用Verilog语言实现CRC-5校验模块,仿真结果与理论分析一致,达到了预期设计的目标。提高了通信的速度、可靠性和效率。     

信号检测中存储控制模块的FPGA设计及实现

文中从MSK跳频信号检测中存储控制模块的FPGA实现入手,分析了如何从存有信号和噪声的存储器中读出一段需要的数据,给出了其FPGA实现方法,并对该方法在实现中所用到的技巧及其在其他领域所具有的适用性作了说明.     

基于智能卡标准的循环冗余校验码的研究与实现

分析了国内外智能卡应用中CRC校验方法的异同,深入研究了智能卡标准及CRC生成多项式,并把CRC的两种计算类型融合在一起,结合智能卡标准中CRC校验的特点提出了一种新的CRC计算模块的硬件实现方法．根据此方法完成了一种CRC计算模块的硬件设计,对设计进行了RTL仿真验证,通过了FPGA验证,并实施了投片．该芯片已经通过流片测试,结果表明模块功能和性能达到设计指标,性能良好．     

CRC32在光通信系统中的快速计算

文章利用C 编程建立了一个可产生CRC32(32位循环冗余校验)各位并行计算的异或表迭式生成模型,并利用Verilog HDL语言在FPGA(现场可编程门阵列)上进行了验证,结果表明,该模型产生的各位异或表达式适合于高速数据传输情况下CRC32的并行计算.     

A Comparison of Some Error Detecting CRC Code Standards

Many data communication systems make use of cyclic redundancy check (CRC) codes for error detection purposes. In this paper, an asymptotic result concerning the undetected error probabilityP(epsilon)of CRC codes is derived. TheP(epsilon)'s of a number of CRC codes which have been adopted as international standards are also examined.     

基于公式递推法的可变计算位宽的循环冗余校验设计与实现

循环冗余校验(CRC)与信道编码的级联使用,可以有效改善译码的收敛特性。在新一代无线通信系统,如5G中,码长和码率都具有多样性。为了提高编译码分段长度可变的级联系统的译码效率,该文提出一种可变计算位宽的CRC并行算法。该算法在现有固定位宽并行算法的基础上,合并公式递推法中反馈数据与输入数据的并行计算,实现了一种高并行度的CRC校验架构,并且支持可变位宽的CRC计算。与现有的并行算法相比,合并算法节省了电路资源的开销,在位宽固定时,资源节约效果明显,同时在反馈时延上也有将近50%的优化;在位宽可变时,电路资源的使用情况也有相应的优化。     

Multiple CRC-aided variable successive cancellation list decoder of polar codes

In order to change the path candidates, reduce the average list size, and make more paths pass cyclic redundancy check (CRC), multiple CRC-aided variable successive cancellation list (SCL) decoding algorithm is proposed. In the decoding algorithm, the whole unfrozen bits are divided into several parts and each part is concatenated with a corresponding CRC code, except the last part which is concatenated with a whole unfrozen CRC code. Each CRC detection is performed, and only those satisfying each part CRC become the path candidates. A variable list is setup for each part to reduce the time complexity. Variable list size is setup for each part to reduce the time complexity until one survival path in each part can pass its corresponding CRC. The results show that the proposed algorithm can reduce the average list size, and the frame error rate (FER) performance, and has a better performance with the increase of the part number.     

Circle-Based Criteria for Performance Evaluation of Controlled DC–DC Switching Converters

An experimental method is proposed to estimate all design specifications represented by circles in the Nyquist plane (e.g., phase margin, sensitivity, and closed-loop bandwidth) in case of closed-loop dc/dc switching converters. The method is based on the complete root contour (CRC) analysis in the root locus plane. All typical specifications for controller design are experimentally checked in case of a boost converter, using only input/output data. The main innovation of this paper is the automatic and systematic application of the CRC method to controlled dc-dc converters. The classic relay-based structure for an experimental estimation of the critical parameters (autotune variation) is compared with a different technique, called sinusoidal autotune variation, more efficient in the case of nonlow-pass systems     

Improvement of CRC receiving controller for serial RapidIO

Serial RapidIO (SRIO) is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check (CRC). In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed. Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resource consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. By comparison to conventional structures, the proposed scheme can achieve better performances. Therefore, this improved receiving controller is considered applicable in high-performance SRIO interconnections.     

Study on cognitive DF relaying cooperation with the mutual interference between primary and secondary users over Nakagami‐m fading channels

In this paper, the cognitive relay cooperation (CRC) wireless communication systems are investigated over Nakagami‐m fading channels. The decode‐and‐forward (DF) relay is employed to assist the communications between cognitive source and destination. Especially, to achieve full diversity order, we consider the case in which there is a direct path between cognitive source and destination. Besides the interference at primary users (PUs) created by secondary users (SUs), the interference at SUs created by PUs is also considered. For the interested CRC systems, we first achieve the exact expression for the CDF of the equivalent end‐to‐end signal‐to‐interference ratio (SIR) of CRC systems. Then, with the exact CDF, the exact average symbol error ratio (SER) and outage performance of CRC systems are achieved. The derivation is of significance, by which we can obtain a detailed knowledge about CRC systems. Though a single integral included in the derivation, it can be calculated numerically by employing some mathematical tools such as Matlab. At the same time, to obtain the insight and highlight the effect of system parameters on the considered CRC systems, by using the high SIR approximation, we obtain the asymptotic closed‐form expression of CDF as well as the ones of average SER and outage probability. From the asymptotic results, we can find the main factors that dominate the performance of CRC systems. The presented simulation results for outage probability and average SER show the derivations and simulations are in agreement. Moreover, in high SIR the achieved asymptotic results match well the exact ones. As a result, in high SIR we can employ the asymptotic closed‐form solutions to evaluate the exact performance of CRC systems. This can reduce greatly the implementation complexity. Besides this, the simulations also show that the diversity order is dominated by the fading severities of the secondary systems, i.e. the diversity order be proportional to the summation of the minimum fading severity between the two hops and that of the direct link. In contrast, the parameters of the primary systems only affect the coding gain, not the diversity gain. Copyright © 2014 John Wiley & Sons, Ltd.     

数据传输系统中CRC校验的DSP算法实现

循环冗余校验码是一种重要的循环码,编码和解码方法简单,容易实现,检错能力强,误判概率几乎为零,是一种效率极高的差错控制方法,可以满足通信系统可靠传送信息的要求,在测控及数据通信中得到了非常广泛的应用。详细介绍了循环冗余校验的编解码原理,分析了用DSP实现CRC的合理性,最后给出了根据校验原理实现的设计思想及流程图,具有一定的实用价值。     

Performance of checksums and CRCs over real data

Checksum and cyclic redundancy check (CRC) algorithms have historically been studied under the assumption that the data fed to the algorithms was uniformly distributed. This paper examines the behavior of checksums and CRCs over real data from various UNIX file systems. We show that, when given real data in small to modest pieces (e.g., 48 bytes), all the checksum algorithms have skewed distributions. These results have implications for CRCs and checksums when applied to real data. They also can cause a spectacular failure rate for both the TCP and ones-complement Fletcher (1983) checksums when trying to detect certain types of packet splices. When measured over several large file systems, the 16 bit TCP checksum performed about as well as a 10-bit CRC. We show that for fragmentation-and-reassembly error models, the checksum contribution of each fragment are, in effect, colored by the fragment's offset in the splice. This coloring explains the performance of Fletcher's sum on nonuniform data, and shows that placing checksum fields in a packet trailer is theoretically no worse than a header checksum field. In practice, the TCP trailer sums outperform even Fletcher header sums     

Adapting standardized CRC codes to support byte structure

Standardized CRC codes used in today’s communication, data storage and process automation systems have odd maximum blocklength, which does not comply with a byte-structure of data where the number of information bits and parity bits is a multiple of eight. To achieve byte-structure, the code’s information part is lengthened by one bit, but without degradation of the code’s minimum distance.