40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW

A bandpass modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 . The power consumption is 16 mW with 1.8 V supply.     

A Silicon Plasma-Based Wideband Modulator

Theoretical and experimental analysis has been performed for surface oriented silicon plasma-based p,i,n structures used to control high power level, broadband devices. It is shown that these structures are very promising for their use as modulators in the millimeter and submillimeter wave range.     

一种宽带矢量调制器的设计及其应用

矢量调制器是一种可以同时控制微波信号幅度和相位的器件。本文介绍了一种基于新型微带定向耦合器的宽带矢量调制器。新的耦合器结构克服了传统微带耦合器耦合度低、方向性差的问题,也不需要Lange耦合器复杂的加工工艺,在平衡放大器、移相器和衰减器等场合具有广泛的应用。其次,研究了用串联电感对衰减器中PIN二极管的寄生参数进行补偿的一种简单方法,以改善衰减器衰减量变化时的相位性能。该方法原理简单,可在一定带宽内替代复杂的平衡结构,并给出相近的性能。最后给出了矢量调制器的测试结果和它在自适应天线阵等实际系统中的应用情况,并讨论了用于提高载波和边带抑制、满足高精度要求的校准方法。     

A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters

This paper presents a hybrid switching amplitude modulator for class-E2 EDGE polar transmitters. To achieve both high efficiency and high speed, it consists of a wideband buffered linear amplifier as a voltage source and a PWM switching amplifier with a 2 MHz switching frequency as a dependent current source. The linear amplifier with a novel class-AB topology has a high current-driving capability of approximately 300 mA with a bandwidth wider than 10 MHz. It can also operate on four quadrants with very low output impedance of about 200 at the switching frequency attenuating the output ripple voltage to less than 12 . A feedforward path, a PWM control, and a third-order ripple filter are used to reduce the current burden of the linear amplifier. The output voltage of the hybrid modulator ranges from 0.4 to 3 V for a 3.5 V supply. It can drive an RF power amplifier with an equivalent impedance of 4 up to a maximum output power of 2.25 W with a maximum efficiency of 88.3%. The chip has been fabricated in a 0.35 m CMOS process and occupies an area of 4.7 .     

A 4-W Master–Slave Switching Amplitude Modulator for Class-E1 EDGE Polar Transmitters

For Class-E1 EDGE polar transmitters, we proposed a 4-W master-slave switching amplitude modulator (MS-SAM) for both high efficiency and wide bandwidth. It consists of a combination of two step-down modules with different switching frequencies and different switch sizes. The master module was designed for wide bandwidth and the slave module for high efficiency. The paper also presents a new current-sensing circuit based on a sample-and-hold circuit operable under a high switching frequency (40 MHz). We showed the topologies and operating principles. The chip was fabricated in a standard 0.35-m CMOS process with an area of 6.45 mm . The MS-SAM could drive the amplifiers of up to 4-W RF power in the experiment. We obtained an efficiency of 89%, and the converter's bandwidth was wide enough to meet the EDGE spectral requirements.     

A Hybrid Audio ΔΣ Modulator with dB‐Linear Gain Control Function

A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital‐to‐analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB‐linear fashion. Also, careful chopper stabilization implementation using return‐to‐zero scheme in the first continuous‐time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm². The ΔΣ modulator achieves a dynamic range (A‐weighted) of 97.8 dB and a peak signal‐to‐noise‐plus‐distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from –9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns_RMS external clock jitter.     

24Gb/s GaAs PHEMT激光二极管/调制器驱动器

采用0.2μm GaAs PHEMT工艺设计并实现了超高速光纤通信系统用激光二极管/调制器集成驱动器电路.整个电路由带源极跟随器的两级差分放大电路、电容耦合电流放大器和输出电路组成.电路芯片面积为1.0mm×0.9mm.测试结果表明,采用单一 5V电源供电时直流功耗为1.5W,输出最高电压幅度为2.4V,电路最高工作速率高于24Gb/s,可以应用于光纤通信SDH(synchronous digital hierarchy)传输系统.     

24Gb/s GaAs PHEMT激光二极管/调制器驱动器

采用0.2μm GaAs PHEMT工艺设计并实现了超高速光纤通信系统用激光二极管/调制器集成驱动器电路.整个电路由带源极跟随器的两级差分放大电路、电容耦合电流放大器和输出电路组成.电路芯片面积为1.0mm×0.9mm.测试结果表明,采用单一+5V电源供电时直流功耗为1.5W,输出最高电压幅度为2.4V,电路最高工作速率高于24Gb/s,可以应用于光纤通信SDH(synchronous digital hierarchy)传输系统.     

一种适合高速接收机的帧同步方法

针对高速接收机并行帧同步模糊状态多、假锁概率高的问题,提出了一种改进的帧同步处理方法.该方法通过截取信号中的一段数据进行回放来降低处理速度,减少了帧同步中的模糊状态.对改进方法的帧同步建立时间和性能进行了理论分析和计算.计算数据表明,新方法在硬件资源和帧同步时间变化不大的情况下使假同步概率减小为原来的1/PM,改善了接收机性能.     

一种低脉冲抖动高速光纤声光调制器

该文分析了调制后光脉冲信号时域抖动的机理,并介绍了低脉冲抖动光纤声光调制器的设计方法.实验验证表明,在波长1550 nm下可得到光脉冲抖动为1.3 ns,光脉冲上升时间为7.9 ns,插入损耗为2.9 dB,消光比为56 dB的高性能光纤声光调制器.     

60-GHz Integrated-Circuit High Data Rate Quadriphase Shift Keying Exciter and Modulator (Short Papers)

An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modulator packaged into a small volume of 1.8x2.5X 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.     

A 0.5-V Wideband Amplifier for a 1-MHz CT Complex Delta-Sigma Modulator

This brief presents a fully differential wideband amplifier for 0.5-V supply. The amplifier employs a gate-input two-stage topology and a dc common-mode feedback circuit with a Miller-amplified capacitor for frequency compensation. Designed in a 130-nm triple-well complementary metal–oxide–semiconductor process with regular $V_{T}$ transistors, the amplifier achieves a simulated performance of 51-dB dc open-loop gain, 112-MHz unity gain bandwidth, and 67 $^{ circ}$ phase margin with a load of 6.5 pF/19.6 $hbox{k}Omega$ , and consumes 600 $muhbox{W}$ at 0.5-V supply. The proposed amplifier is incorporated in a continuous-time complex Delta-Sigma modulator with a 1-MHz signal bandwidth and 64$times$ oversampling ratio. In the simulations, the modulator achieves a 72.5-dB signal-to-noise-plus-distortion ratio and consumes 2.3 mW at 0.5 V.      

Wideband, Low Driving Voltage Traveling-Wave Mach–Zehnder Modulator for RF Photonics

We report the design, fabrication, and testing of a traveling-wave Mach-Zehnder modulator on a GaAs substrate. Operating at 870-nm wavelength, we obtained an extremely low driving voltage of 0.45 V and a high measurement-instrument-limited small-signal modulation bandwidth of 18 GHz, projected to an estimated bandwidth of 50 GHz. We have also monolithically integrated photodetectors with an impulse response of 8-ps full-width at half-maximum, and a saturation power of 330 mW, giving a flexible high-performance platform for RF photonics.     

A Novel Architecture of Delta-Sigma Modulator Enabling All-Digital Multiband Multistandard RF Transmitters Design

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex.      

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 $muhbox{m}$ CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 $~$dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).      

Switching rates of two-branch selection diversity in κ-μ and α-μ distributed fadings

An analytical expression for the switching rate of a dual branch selection diversity combiner in κ-μ and α-μ distributed fadings is derived. Independent and identically distributed (i.i.d.) κ-μ as well as α-μ fading channels are considered. The switching rates for dual i.i.d. Rayleigh, Rician and Nakagami-m fading channels are special cases of the switching rate for dual i.i.d. κ-μ fading channels. Similarly, the general switching rates for dual α-μ fading channels also include special cases such as Rayleigh, Nakagami-m, and Weibull fading channels.     

适于长距离、高速率光纤通信系统的Ti：LiNbO_3M－Z型强度调制器

本文报道了１．５μｍ波长高速Ｔｉ：ＬｉＮｂＯ_３Ｍ－Ｚ型强度调制器的设计、制作、封装和检测。所得包装式器件的性能指标为：插入损耗６．７ｄＢ，开关电压７．３Ｖ，３ｄＢ调制带宽８ＧＨｚ，消光比—２１ｄＢ。     

一种宽带、低失真、高过载特性的Sigma-Delta模数转换器结构

提出一种混合Sigma-Delta级联调制器结构.结合传统和低失真结构的优点,包括4级:第一级采用二阶多位低失真结构,后面级联传统的一阶调制器.这种结构可以大大减小由于第一级调制器输入信号过大引起的非线性,同时可以较好地抑制带内噪声,因而非常适用于低过采样率和高精度的转换器设计.仿真结果表明,混合Sigma-Delta级联调制器结构具有高的过载特性、节省功耗和芯片面积等优点,适合宽带宽领域的应用.     

超宽带高速数据传输技术研究

为了解决超宽带（UWB）高速数据传输中的硬件处理速度瓶颈、码间干扰和多径影响等问题,可采用多个伪码并行调制传输的方法,该方法可以有效提高超宽带系统的传输速率,降低码间干扰和实际工程处理难度。经过对多伪码并行超宽带信号的调制发射、接收解调的性能分析,并通过实物试验,验证了其工程可实现性。与DS-UWB系统相比,在相同的传输带宽下,提高了信息速率,但这是以设备的复杂度增大为代价的。     

一种高速数传接收机的高效维特比译码结构设计

在高速数传接收机中,通常采用并行解调结构,解调后的数据以多路并行的方式送给译码单元,因此对应的译码也需采用相应的结构。本文设计了一种并行的维特比译码架构,降低现场可编程阵列(FPGA)器件的处理速率,以适应高速接收机的应用。