A 40 ns 64 kbit junction-shorting PROM

The memory is organized as 8192 words/spl times/8 bits. A memory cell consists of a programmable element composed of a p-n junction diode and a vertically connected p-n-p transistor. During programming, the programmable element is changed from the current-blocking state of a reverse diode to the current-conducting state of a shorted junction diode by using the diffused eutectic aluminum process (DEAP). With a selective power switching dual-stage decoder, the power dissipation in the decoder circuit was reduced to 40% of a conventional decoder without power switching. The power saved was used to speed up the multiplexers and the output buffers.     

A high speed 16 kbit ECL RAM

A 16384 /spl times/ 1 bit ECL RAM (emitter coupled logic random access memory) with an access time of 15 ns and a power dissipation of 700 mW has been developed. The high packing density and performance were achieved by using a p-n-p load cell, a novel ECL circuit, and U-groove isolation. The test results proved that a p-n-p load cell is very effective in producing a fast high-density bipolar RAM having a capacity of over 64 Kbits.     

A low power resistive load 64 kbit CMOS RAM

A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral circuits with address transition detectors are implemented to achieve high speed and low power simultaneously. A new CMOS fault-tolerant circuit technology is also introduced for improving fabrication yield without sacrificing operating speed or standby power. The resulting cell size and die size are 15/spl times/19 /spl mu/m and 4.87/spl times/7.22 mm, respectively. The RAM offers, typically, 70 ns access time, 15 mW operating power, and 10 /spl mu/W standby power.     

64 kbit/s audio signal transmission approaches using 32 kbit/sADPCM channel banks

Two simple 64-kb/s wideband coding approaches using 32-kb/s ADPCM (adaptive digital pulse-code modulated) channel banks are proposed and compared to CCITT 64 kb/s ADPCM, which is being recommended as CCITT G.722. These two, folding ADPCM and QMF ADPCM, are intended to pave the way for smooth transition from conventional 4-kHz band telephone systems to 7-kHz wideband systems in private networks. The first approach, supporting the high-quality audio program transmission, requires only samplers and multiplexers at the input and output ports of the channel banks. In the second approach, samplers and multiplexers are replaced by quadrature mirror filters in order to increase coding quality. Performance test results for audio signal transmission show that these simplified approaches provide an inexpensive way to introduce wideband communication systems     

A 16 kbit smart 5 V-only EEPROM with redundancy

This paper describes several circuit techniques used in the design of a 5-V-only 16 Kbit EEPROM. The EEPROM uses a two transistor cell based on Fowler-Nordheim tunneling to a floating polysilicon gate. The EEPROM features 5-V-only operation, a self-timed program cycle with automatic erase before write, address and data latches, and a `ready' line output. These features make the program cycle timing compatible with static RAMs and simplifies the microprocessor interface. A new redundancy technique using EE cells as the programming element is also described.     

A 64 kbit/s Videophone codec with forward analysis and control

A new combination of coding methods for a 64 kbit/s transmission system for typical videophone situations is investigated. The codec structure is based on a standard hybrid discrete cosine transform (DCT) codec with temporal prediction. The picture is divided blockwise into changed and unchanged areas. One motion vector with subpel accuracy is computed and transmitted for each block of the changed area. For the forward analysis, the prediction error is calculated in the whole picture. Only the blocks with the highest prediction errors are updated by a DCT with a perception adaptive quantization. The number of DCT update blocks depends on the remaining bits after the transmission of the overhead information. The codec is controlled by a forward analysis of the prediction error and is not based on a buffer control. The spatial resolution of the source signal is reduced in two steps to prevent a codec overload caused by too much activity between two frames.     

一种基于SBC技术的16kbit/s高效语音编译码器

本文介绍一种基于SBC技术的16kbit／s高效语音编译码器．在该编码方案中，IIR型正义镜象滤波器（QMF）用于实现语音分带，而基于快速搜索技术的矢量量化（FVQA）用于对除基带（采用ADPCM技术）外的其余高频带语音编码。一片TMS320C25芯片实现了两路16kbit／s语音编译码器，并借此实现了两人双向实时通信。得到良好的语音可懂度、自然度及客观评测结果。     

GaAs 1 kbit static RAM with self-aligned FET technology

A GaAs-1 kbit RAM is demonstrated to realize high-speed switching at the LSI level. The SAINT FET is utilized to eliminate the surface depletion without an increase of excess capacitance. To lower the threshold voltage standard deviation, a one-direction gate arrangement is adopted. A pull-up circuit is also a new addition to the first reported RAM. The resulting RAM performances are 1.5 ns address access time with 369 mW power consumption. The minimum write-enable pulsewidth is less than 2 ns. The maximum number of good bits is 1001 bits/1024 bits. The problems of mass production of GaAs LSI are discussed.     

A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects.     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

High quality audio transform coding at 64 kbit/s

This paper presents a transform coding algorithm designed for audio coding at a bit rate of 64 kbit/s. It enables the transmission of a high quality stereo sound through the 2B channels of isdn. Although a complete system including framing, synchronization and error correction has been developed, only the bit rate compression algorithm is described here. A detailed analysis of the signal processing techniques such as the time/frequency transformation, the preecho reduction by adaptive filtering, the fast algorithm computations…, is provided. The use of psychoacoustical properties is also precisely reported. Finally, some subjective evaluation results and one real time implementation of the coder using the att dsp52c digital signal processor are presented.     

A 64 kbit/s Integrated Visual Communication System--New Communication Medium for the ISDN

Seeing-while-talking has been a dream of mankind for over a 100 years since the invention of telephone. In the past, various trials were performed in spite of the difficulty in installing the network for the actual service. However, with the progress of ISDN and the advancement of digital signal processing technology, the environment has been changing rapidly. In this paper, an integrated visual communication system is described for the enhanced communication service at 64 kbits/s, the fundamental bit rate of ISDN. The roles of state-of-theart compression of the audio and video signals are discussed and an integrated transmission method based on the priority of the information content is proposed.     

New error recovery strategy for 64 kbit/s video codecs

A new error recovery strategy for 64 kbit/s video codecs is described. Unlike existing strategies of error recovery in which a new frame is transmitted on the detection of a channel error, the new strategy uses previous frames which are known to be correct. Computer simulations of the technique are performed and subjective and quantitative results are obtained     

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.     

APC-AB codec modules operating at 16 and 8 kbit/s

High-quality speech codec modules operating at 16 and 8 kb/s have been developed using an adaptive predictive coding with adaptive bit allocation (APC-AB) scheme. An optimized APC-AB algorithm is studied that reduces processing complexity while maintaining speech quality. The coding algorithm is implemented in two digital signal processors (DSPs). The DSP chips, a framing LSI circuit, a PCM codec, and some peripheral ICs are integrated in each of two compact packages, i.e. codec modules, operating at 16 or 8 kb/s. The codec module size is as small as 80 mm×50 mm×12 mm, and its typical power consumption is 500 mW using 2-μm CMOS LSI technology. At 16 kb/s this APC-AB codec achieves high speech quality, close to that of a 7-bit μ-law PCM. The codec modules are expected to be used for various applications such as customer premises multiplexers for digital leased lines, digital mobile radio, and stored-and-forward-message systems (voice-mail systems)     

A 64K DRAM with 35 ns static column operation

A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.     

Evaluation of 16 kbit/s digital voice transmission for mobile radio

In this paper 16 kbit/s digital voice transmission with conventional channel spacing of 25 kHz, employing a 16 kbit/s adaptive delta modulation (ADM) coder-decoder (CODEC) is evaluated. The main characteristics of narrow-band digital FM modulation schemes, such as tamed FM, Gaussian filtered minimum shift keying (GMSK), four-level FM and phase locked loop-quaternary phase shift keying (PLL-QPSK), are compared by laboratory tests. Digitized voice quality in a digital channel incorporating a 16 kbit/s ADM CODEC and GMSK coherent detection was compared with voice quality of a conventional analog FM channel. Bit error ratio (BER) performance is shown to depend primarily on demodulation schemes. Digital voice quality is inferior to that of analog voice with an opinion score difference of about 0.5 in fading environments. This kind of digital voice transmission will be applicable for those systems that require high security at an expense of speech quality.     

A 35 ns 16K NMOS static RAM

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.     

16kbit/s分带自适应预测语音压缩系统中的正交镜象滤波器

本文讨论了16kbit/s分带自适应(SB—APC)预测语音压缩编码系统中的正交镜象滤波器(QMF)的原理和设计过程,并给出了实现QMF的硬件和软件结构。