Comments on “High Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm”

We have a number of issues with the above paper ldquoHigh Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Current Exceeding 1 A/mm,rdquo by Y. Xuan, Y. Q. Wu, and P. D. Ye, published IEEE Electron Device Letters in April 2008 which we wish to highlight.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

增强型InGaP／AlGaAs／InGaAs PHEMT栅退火工艺

针对InGaP/AlGaAs/lnGaAs PHEMT器件,进行了Ti/Pt/Au和Pt/Ti/Pt/Au两种栅金属结构的退火实验,通过实验研究比较,得到了更适用于增强型器件的退火工艺,利用Ti/Pt/Au结构,在320℃退火40min,使器件阈值电压正向移动大约200mV,从而成功制作了高成品率的稳定一致的增强型器件,保证了增强型器件阈值电压在零以上.     

1-μm Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm

In this letter, 1-mum GaAs-based enhancement-mode n-channel devices with channel mobility of 5500 cm²/Vmiddots and g _m exceeding 250 mS/mm have been fabricated. The measured device parameters including threshold voltage V_th, maximum extrinsic transconductance g_m, saturation current I_dss , on-resistance R_on, and gate current are 0.11 V, 254 mS/mm, 380 mA/mm, 4.5 Omegamiddotmm, and < 56 pA for a first wafer and 0.08 V, 229 mS/mm, 443 mA/mm, 4.5 Omegamiddotmm, and < 90 pA for a second wafer, respectively. With an intrinsic transconductance g_mi of 434 mS/mm, GaAs enhancement-mode MOSFETs have reached expected intrinsic device performance     

Double-side planar-doped AlGaAs/InGaAs/AlGaAs MODFET with currentdensity of 1 A/mm

AlGaAs/InGaAs/AlGaAs double-side planar-doped (DSPD) pseudomorphic MODFETs of 0.3-μm gate length with both excellent DC and RF performances are reported. A maximum unilateral gain cutoff frequency of 170 GHz and a maximum current gain cutoff frequency of 60 GHz are achieved. The devices exhibit a maximum transconductance of 500 mS/mm and an extremely high current density of 1 A/mm. These are the highest frequencies reported so far for MODFET devices capable of driving 1-A/mm current density. This current density is the highest ever reported with this type of layer structure     

High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.      

AlN/GaN Insulated-Gate HEMTs With 2.3 A/mm Output Current and 480 mS/mm Transconductance

High-electron mobility transistors (HEMTs) based on ultrathin AlN/GaN heterostructures with a 3.5-nm AlN barrier and a 3-nm $hbox{Al}_{2}hbox{O}_{3}$ gate dielectric have been investigated. Owing to the optimized AlN/GaN interface, very high carrier mobility $(sim!!hbox{1400} hbox{cm}^{2}/hbox{V}cdothbox{s})$ and high 2-D electron-gas density $(sim!!kern1pthbox{2.7} times hbox{10}^{13} /hbox{cm}^{2})$ resulted in a record low sheet resistance $(sim !!hbox{165} Omega/hbox{sq})$. The resultant HEMTs showed a maximum dc output current density of $simkern1pt$2.3 A/mm and a peak extrinsic transconductance $g_{m,{rm ext}} sim hbox{480} hbox{mS/mm}$ (corresponding to $g_{m,{rm int}} sim hbox{1} hbox{S/mm}$). An $f_{T}/f_{max}$ of 52/60 GHz was measured on $hbox{0.25} times hbox{60} muhbox{m}^{2}$ gate HEMTs. With further improvements of the ohmic contacts, the gate dielectric, and the lowering of the buffer leakage, the presented results suggest that, by using AlN/GaN heterojunctions, it may be possible to push the performance of nitride HEMTs to current, power, and speed levels that are currently unachievable in AlGaN/GaN technology.      

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

A new RF trench-gate multi-channel laterally-diffused MOSFET on InGaAs

In this work, a new RF power trench-gate multi-channel laterally-diffused MOSFET (TGMC-LDMOS) on InGaAs is proposed. The gate-electrodes of the new structure are placed vertically in the trenches built in the drift layer. Each gate results in the formation of two channels in the p-body region of the device. The drain metal is also placed in a trench to take contact from the n⁺-InGaAs region located over the substrate. In a cell length of 5 μm, the TGMC-LDMOS structure has seven channels, which conduct simultaneously to carry drain current in parallel. The formation of multi-channels in the proposed device increases the drive current (I_D) leading to a large reduction in the specific on-resistance (R_on-sp). Due to better control of gates on the drain current, the new structure exhibits substantially higher transconductance (g_m) resulting in significant improvement in cut-off frequency (f_T) and oscillation frequency (f_max). Using two-dimensional numerical simulations, a 55 V TGMC-LDMOS is demonstrated to achieve 7 times higher I_D, 6.2 times lower R_on-sp, 6.3 times higher peak g_m, 2.6 times higher f_T, and 2.5 times increase in f_max in comparison to a conventional device for the identical cell length.     

高性能1mm SiC基AlGaN/GaN功率HEMT研制

在6H-SiC衬底上,外延生长了AlGaN/GaN HEMT结构,设计并实现了高性能1mm AlGaN/GaN微波功率HEMT,外延材料利用金属有机物化学气相淀积技术生长.测试表明,该lmm栅宽器件栅长为0.8μm,输出电流密度达到1.16A/mm,跨导为241mS/mm,击穿电压＞80V,特征频率达到20GHz,最大振荡频率为28GHz.5.4GHz连续波测试下功率增益为14.2dB,输出功率达4.1W,脉冲条件测试下功率增益为14.4dB,输出功率为5.2W,两端口阻抗特性显示了在微波应用中的良好潜力.     

高性能1mm SiC基AlGaN/GaN功率HEMT研制

在6H-SiC衬底上,外延生长了AlGaN/GaN HEMT结构,设计并实现了高性能1mm AlGaN/GaN微波功率HEMT,外延材料利用金属有机物化学气相淀积技术生长.测试表明,该lmm栅宽器件栅长为0.8μm,输出电流密度达到1.16A/mm,跨导为241mS/mm,击穿电压＞80V,特征频率达到20GHz,最大振荡频率为28GHz.5.4GHz连续波测试下功率增益为14.2dB,输出功率达4.1W,脉冲条件测试下功率增益为14.4dB,输出功率为5.2W,两端口阻抗特性显示了在微波应用中的良好潜力.     

Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance

Strained p-MOSFETs with silicon-germanium (SiGe) source and drain (S/D) stressors were fabricated on thin-body silicon-on-insulator (SOI) substrate using a novel local oxidation or Ge condensation technique. By directly growing SiGe on the S/D regions and followed by a local Ge condensation process, the challenges imposed on Si recess etch on thin-body SOI substrates can be alleviated. In the Ge condensation step, the Ge content in the S/D regions may also be increased. At a gate overdrive of -1 V, strained p-MOSFETs show an enhancement in the saturation drive current I_on of up to 38% over the control p-MOSFETs. This significant I_on enhancement is attributed to strain-induced band structure modification, which reduces the hole effective mass along the transport direction. The improved series resistance of the strained devices with SiGe S/D accounted for approximately one-third of the I_on enhancement.     

我国研制成功面向3mm波段的InGaAs/InP双异质结双极型晶体管

近日,中国科学院微电子研究所微波器件与集成电路研究室（四室）金智研究员领导的课题组成功研制出面向3mm波段的InGaAs／InP双异质结双极型晶体管。     

Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD$hboxHfO_2$has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation.     

一个适用于RFIC设计的RF MOSFET源漏电阻可缩放模型

提出了一个可用于0.18 μm CMOS工艺RF-MOSFET的源漏电阻的可缩放模型.采用了一种直接基于S参数测量的方法来准确提取端口的寄生电阻,该模型充分考虑了各种版图尺寸,如沟道长度,沟道宽度和栅极指头数目等参数的可缩放性.此后,该模型通过不同尺寸的共源连接RF MOSFET的测量和仿真的直流、小信号S参数特性比对,曲线达到了较好的吻合,表明我们的模型是精确而且有效的.     

A nanoanalytical investigation of the Ga2O3/GaGdO dielectric gate stack for InGaAs based MOSFET devices

In this paper, a subnanometer characterization of the Ga₂O₃/GdGaO dielectric gate stack grown on top of InGaAs lattice matched to n⁺ InP substrate is presented. The paper shows the analysis of two samples grown using different substrate temperature. This clearly affects the electrical characteristics as well as the photoluminescence properties. The paper also describes how the growth conditions of oxide stack affect the elemental distribution across the interface region.     

A 1-V CMOS D/A converter with multi-input floating-gate MOSFET

A low-voltage D/A converter using multi-input floating-gate MOSFET within a matrix current cell architecture is described in this paper. The two-input floating-gate p-channel MOSFET of each current cell performs the combined functions of current source and current switch. The double-gate-driven MOSFET circuit technique was employed in the digital circuitry to facilitate low supply voltage operation. A 6-bit and 8-bit digital-to-analog converter (DAC) have been fabricated in standard double-poly double-metal 1.2 μm CMOS technology. Measurements show a supply voltage as low as 0.9 and 1.0 V is sufficient to operate the 6-bit and 8-bit DAC, respectively, with a 5 Msamples/s conversion rate     

Normally Off AlGaN/GaN Low-Density Drain HEMT (LDD-HEMT) With Enhanced Breakdown Voltage and Reduced Current Collapse

We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (f_t) and slight improvement in power gain cutoff frequency (f_max) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode     

低漏电高增益InGaAs/InP SAGM雪崩光电二极管

根据器件结构的优化设计,严格控制生长参数以及理想的器件制备工艺获得了低漏电高增益InGaAs/InP SAGM雪崩光电二极管。测量了百余支器件,0.9V_b下漏电流I_d<20nA;响应度～(0.7—0.8)mA/mW,最大倍增30—85(入射光波长1.3μm,功率1.6μW),参与倍增的暗电流l_(dm)最小可达0.25nA。     

Drain current dlts analysis of recoverable and permanent degradation effects in AlGaAs/GaAs AND AlGaAs/InGaAs HEMT'S

We present a detailed study of drain current DLTS spectra performed on asreceived and failed AlGaAs/GaAs and AlGaAs/InGaAs HEMT's of four different suppliers submitted to hot-electron tests. We demonstrate that a remarkable correlation exists between DLTS features and permanent and recoverable degradation effects. In particular, different behaviours have been found: (i) recoverable effects seems to be correlated with modulation of charge trapped on DX and ME6 centers. (ii) permanent degradation consisting in a decrease in Id and V_T is due to negative charge trapping and is associated with a large increase of a peak having Ea=1.22 eV in the DLTS spectra of failed devices; (iii) development of traps in the gate-to-drain access region induces a permanent increase in drain parasitic resistance Rd and decrease in Id, and is correlated with the growth of a “hole-like” peak in DLTS spectra measured after hot-electron tests.