Charge storage effects in silicon dioxide films

The dc properties of the system Si:SiO2(6000 Å), metal have been investigated at 200-400°C. The system shows unidirectional conduction at 400°C. Little or no current is observed when the silicon electrode is positive. There is a region of reversible charge storage and discharge at negative silicon voltages; the center of this region is around -2 volts when the contact metal is gold, but more positive when it is aluminum. The quantities of charge stored range from 4 × 10¹²to 2 × 10¹⁴charges/cm². At still more negative silicon voltages there is a region of ohmic conduction, the resistivity at 400°C ranging from 10¹²to 10¹⁴Ω-cm. The charge storage, which is far greater than that anticipated from the oxide capacitance, can be shown to occur principally in the oxide under the metal contact, and not over a broad adjacent area. Storage of charge in the oxide causes ann-type shift of the underlying silicon surface. Charges can develop in the oxide as a result of nonelectrical processes, such as high-temperature gas baking treatments. Conversion of the upper 600 Å of the oxide to a phosphate glass eliminates both charge storage and ohmic conductivity in the oxide. The results described are interpreted in terms of an electrochemical potential existing across the oxide, and the presence of mobile charged species within the oxide. Charge storage can occur as the result of double-layer formation by the mobile charged species, or of its electrochemical discharge at the electrodes. The unidirectionality of the ohmic conduction is considered to result from electrolytic rectification at the silicon-oxide boundary.     

Theory, design, and performance of low-blooming silicon diode array imaging targets

The increase in size of an image produced by a high intensity source is particularly troublesome in silicon diode array imaging devices. This increase is caused by inversion of Si under the SiO2between the diodes or by the lateral diffusion of the excess minority carriers in the field-free region of the sensor array. The formation of inversion layers can be eliminated by proper choice of the sheet resistance of the resistive sea when the target is operated above flat-band voltage. However, when the diodes in the image are fully discharged in a time interval shorter than the frametime, the excess carriers diffuse to the adjacent diodes and cause an increase in the size of the image. Such "blooming" is related to the effective minority carrier lifetime that is a function of surface recombination velocity at the imaging side of the target, surface recombination velocity at the diode side of the target, and bulk minority carrier lifetime. Two methods for controlling blooming will be discussed. In one case, the effective minority carrier lifetime is reduced by adjusting the n⁺doping profile at the imaging side of the array. The second technique requires diffusion of a separate p-type region, placed between the sensing diodes elements, which provides a high recombination region when the sensing diodes are discharged due to the image overload. Devices have been constructed with good imaging quality, where a 1 percent scan diagonal bright spot bloomed to 4 percent in the first technique, and to 2.5 percent in the second technique with a 10⁵overload above saturation. The data are in good agreement with the theory.     

The Epicon™camera tube: An epitaxial diode array vidicon

The structure and processing of epitaxial silicon diode array targets for vidicon camera tubes are described with emphasis on the way they differ from conventional silicon diode array targets. These targets, called Epicon^™vidicon targets, are generally similar to other silicon vidicon targets, but have the p-type boron diffused islands replaced by pyramidal or mesa-like structures that extend through the oxide apertures and up and over the oxide. The target is a self-registered conducting cap-type structure and does not require a resistive sea for its operation. It has some additional advantages in its structure and its processing over the other silicon diode array target. A comparison of the results of some selective epitaxy processes is briefly made. Some of the operating characteristics of the tube are described.     

Electron microprobe analysis of impurity heterogeneities in thermally grown silicon oxide

The electron probe X-ray microanalyzer is a powerful tool for studying impurity distribution and motion in thin films. This analytical instrument is capable of detecting metallic impurities present in areas as small as 1 × 10^-6mm²and in concentrations of greater than 1 × 10¹⁹atoms/cm³. The analysis requires no sample preparation and is essentially a nondestructive test. This instrument was used to examine unoxidized and oxidized silicon surfaces and a finished microcircuit. With the electron microprobe, aluminum-bearing regions approximately one microns in diameter were detected on the bare surface of mechanically polished silicon slices. These aluminum-rich regions are believed to be alumina abrasive used in polishing. If these regions are not removed by chemical etching they will generate oxide defects during oxidation. These defects were found to contain Al (1 × 10²¹atoms/cm³and Na (1 × 10²⁰atoms/cm³). Other oxide defects, i.e., pinholes, generated during oxidation varied in size from 0.5 to 5.0 microns and were found to contain Na (1×10²¹atoms/cm³) and K (5×10²¹atoms/cm³). Mg and Ca (1 × 10²⁰atoms/cm³) were occasionally observed in these defects. After oxidation, all these impurities could be removed with a hot hydrochloric acid and deionized water rinse; surprisingly, this treatment reduced the silicon surface charge in the MOS structure (X_{0} cong 1500Å) by approximately 1.4 × 10¹¹charges/cm². The surface charge could be further reduced by heating the oxidized wafer at 900°C in a silicon nitride tube.     

Positive flatband voltage shift in MOS capacitors on n-type GaN

GaN MOS capacitors were fabricated using silicon dioxide deposited by low-pressure chemical vapor deposition oxide at 900°C. The MOS capacitor flatband voltage shift versus temperature was used to determine a pyroelectric charge coefficient of 3.7 × 10⁹ q/cm²-K, corresponding to a pyroelectric voltage coefficient of 7.0 × 10⁴ V/m-K     

C-V Characteristics of GaP MOS diode with anodic oxide film

Gallium phosphide was anodically oxidized in an aqueous H2O2solution and MOS diodes were fabricated by the evaporation of aluminum. The resistivity and electric breakdown strength were higher than 10¹⁴Ω.cm and 6 × 10⁶V/cm, respectively. Almost no frequency dispersion was observed in the C-V curves from 100 Hz to 1 MHz. The C-V curve showed the injection-type hysteresis. From the hysteresis window, the transferred charged carriers were estimated to be about 9 × 10¹¹/cm². By leaving the diode biased at negative voltage or by shining light with energy higher than 1.8 eV, the curve shifted to negative voltage direction. The results indicate that the density of the fast interface states which follow the 100-Hz signal is very low but there exist deep electron traps with activation energy higher than 1.8 eV near the surface in the oxide film and the shallower electron traps which cause the hysteresis in the dark.     

Buried-guarded layer ion-implanted resistors

Megohm silicon monolithic resistors have been fabricated with sheet resistances up to 120 kΩ/□ using an implanted p-layer resistor which is buried under an implanted n-guard layer. The n-guard layer protects against slice-to-slice variations of the fixed surface charge, and was made using phosphorus doses and energy of 1.5-5 × 10¹²/cm²and 30 keV. Resistors have been fabricated up to 20 MΩ; sheet resistances were in the range of 7-120 kΩ/□ using boron doses and energies of 1-3 × 10^:12/cm²and 30-300 keV. The sheet resistance, voltage dependence of resistance, temperature coefficients, junction leakage, and parasitic capacitance have been measured for different implantation parameters. This process has been used to fabricate two matched 8-MΩ resistors for use in a high input impedance differential preamplifier integrated circuit. A match of 2 percent and a magnitude tolerance of ±10 percent has been achieved. The temperature coefficient of resistance (TCR) is about 4000 ppm/°C and tracks within 400 ppm/ °C. These resistors are linear up to ∼1 V, about 50 times higher bias voltage than required in the application. The structure and fabrication are compatible with present monolithic silicon integrated circuit processing.     

A silicon diode array scan converter for high-speed transient recording

A double-ended scan converter tube has recently been developed which uses a silicon diode array for the storage target. The purpose of the device is to capture high-speed single transients or low-repetition-rate signals and to retain the information until it can be read out at speeds slow enough for handling by conventional processing and display circuits. Improvements in wide-bandwidth deflection and the resolution of both writing and reading guns, combined with a charge gain of 2000 in the target, enables data to be stored at unprecedented rates. Information writing speeds of 2 × 10¹²tracewidths/s are possible with the device, sufficient for displaying a full-screen 2-GHz Sine wave. To reliably digitize the readout for signal processing, a signal-to-noise ratio of about 20:1 is required which the device, will provide at speeds up to 5 × 10¹¹tracewidths/s. Resolution at a 50-percent modulation level is 400 TV lines per horizontal scan (15.7 cycles/mm at the target).     

X-ray imaging camera tube using sputter-deposited CdTe/CdSheterojunction

CdTe heterojunction devices have been fabricated for the first time by an RF sputter deposition method for application to X-ray imaging sensors. The electrical resistivities of sputter-deposited polycrystalline CdS and CdTe films are greater than 10⁶ Ω-cm and 10⁹ Ω-cm, respectively. The fabricated CdS/CdTe heterojunction sensor shows a good diode characteristic and a high sensitivity to X-ray radiation. An X-ray imaging camera tube consisting of CdS/CdTe heterojunction photoconductive target shows three times larger responsivity to X-rays than the conventional PbO X-ray tube. The dark current density of the device is observed to be lower than 10 nA/cm² at 20 V target voltage at room temperature     

Ultra-shallow high-concentration boron profiles for CMOS processing

The fabrication of ultra-shallow high-concentration boron profiles in silicon has been carried out utilizing a XeCl excimer laser. The Gas Immersion Laser Doping (GILD) process relies on a dopant species, in this case diborane (B2H6), to be adsorbed on the clean silicon surface and subsequently driven in during a melt/regrowth process initiated upon exposure to the short laser pulse. Secondary Ion Mass Spectrometry and spreading resistance profiles show peak boron concentrations from 5 × 10¹⁹cm^-3to 5 × 10²⁰cm^-3depending on the number of laser pulses, with junction depths from 0.08 to 0.16 µm depending on the laser energy. Electrical characteristics show essentially ideal diode behavior following a 10-s 950°C anneal.     

Monitoring of low-dose ion implantation in silicon

Monitoring of low-dose arsenic or boron ion implantation (doses: 5×10¹⁰ to 1×10¹³ cm^-2) in silicon, which is required for threshold voltage control of MOS transistors, is studied. The thermal-wave (TW) signal intensity decreases monotonically with decreasing dose. The lowest detection limit for As⁺ and B⁺ implantations is 5×10¹⁰ and 1×10¹¹ cm^-2, respectively. Correlation of the TW signal intensity versus damage density, TW intensity versus dose, and laser Raman intensity versus dose is obtained. The TW intensity is also correlated with the sheet conductance, and the threshold voltage of the transistor. Therefore, this technique is useful as a nondestructive, highly sensitive dose monitor for low-dose implantation to achieve tight threshold voltage control in MOS transistors     

Interface effects of SIPOS passivation

Electrical characterization of metal-semi-insulating polycrystalline silicon (SIPOS)-Si samples have been carried out usingIV,C-V, andC-ttechniques. Bulk resistivity and interface properties have been examined. The results indicate that annealing can give rise to a current barrier at the SIPOS-Si interface that constitutes another mechanism for interface charge formation as distinct from interface states. This current barrier-induced interface charge can lead to significant spreading of the depletion zone on test diodes. With SIPOS bulk resistivity greater than 10⁸Ω . cm, the interface electrical properties are shown to have greater influence than bulk SIPOS properties on device behavior.     

Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors

The deep-depletion breakdown voltage of silicon-dioxide/ silicon MOS capacitors is determined by the ionization-integral method, with potential distributions computed by two-dimensional relaxation techniques. Calculations cover the range of substrate doping between 10¹⁴and 10¹⁸cm^-3and oxide thickness between 0.01 and 5.00 µm, providing plots of breakdown voltage versus substrate impurity concentration with oxide thickness as parameter. A universal and normalized criterion is derived for field uniformity in terms of the ratio of oxide thickness to the maximum (breakdown) width of the silicon depletion region: this ratio should be larger than 0.3 in order not to have field concentration around the edges of the metal plate.     

Composite TiSi2/n + poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2polycide gate. A coevaporated TiSi2polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2because of lower oxygen contamination. The coevaporation technique to form TiSi2polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n+-p silicon diodes

The results of minority-carrier lifetime measurements in heavily phosphorus-doped n⁺diffused layers of p-n junction diodes using a spectral response technique are reported in this paper. Exact modeling of current-flow equations, modified to include bandgap reduction due to high carrier concentration and Auger recombination, is used to compute the dependence of diffused-layer photocurrent Jpthon the incident light energy and intensity. The photocurrent in the diffused layer is also obtained by subtracting the theoretical value of the space charge and uniformly doped p-region component from the experimentally measured photocurrent of the diode at each wavelength. Note that all calculated values based on light intensity include computed transmittance/reflectance through the oxide layer at each wavelength. The comparison of the values of Jpthwith Jpexp, using nonlinear least square techniques, then directly gives the lifetime profile in the diffused layer. A simple expression is given for lifetime as a function of doping which may be used in modeling and prediction of device performance. Using this experimental technique it was found that the lifetime in the diffused layer is an order of magnitude less than that corresponding to uniformly doped bulk-silicon values and is very much process dependent; its value being 3.72 × 10^-11s for surface concentration of 3.0 × 10²⁰cm^-3and increases to 2.9 × 10^-8s at doping concentration of 1.0 × 10¹⁷cm^-3.     

Ring-dot impedance measurement, a simple technique for measuring inversion-layer conductance in semiconductors

Impedance measurements utilizing evaporated ring-dot metal-oxide-semiconductor (MOS) structures are shown to give accurate values of sheet conductance of inversion layers. The well-defined geometry simplifies evaluation of experimentally measured quantities. The results obtained are shown to be independent of the geometry of the test structures and of frequency. Limitations of the technique due to shunting by the substrate are discussed. It is found that for a channel sheet resistance of 10⁴ohms the technique can be used for substrate impurity concentrations up to 5 × 10¹⁶cm^-3in silicon.     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces

Extensive measurements of electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces were performed using the field effect conductance technique. It was found that both electron and hole mobilities are practically constant and approximately equal to one half of their respective bulk values up to a surface field of about 1.5 × 10⁵volts/cm, corresponding to about 10¹²electronic charges/cm²induced in the silicon. At higher fields the inversion layer mobilities begin to decrease slightly. The temperature dependence of inversion layer mobilities follows a T^-1.5rule at the upper range of the interval -196 to 200°C, indicating a scattering mechanism similar to lattice scattering. This observation is further supported by the lack of a significant effect of an order-of-magnitude variation in the bulk impurity concentration (10¹⁵- 10¹⁶cm³) on the inversion layer mobilities. No significant effect of structural and geometrical parameters (such as channel length and shape, oxide type and thickness, and surface charge density) was found on the inversion layer mobilities.     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.