Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

In this paper, a pixel structure called the optimal pseudoactive pixel sensor (OPAPS) is proposed and analyzed for the applications of CMOS imagers. The shared zero-biased-buffer in the pixel is used to suppress both dark current of photodiode and leakage current of pixel switches by keeping both biases of photodiode and parasitic pn junctions in the pixel bus at zero voltage or near zero voltage. The factor of photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined to characterize the performance of the OPAPS structure. It is found that a zero-biased-buffer shared by four pixels can achieve the highest PDRPA. In addition, the column sampling circuits and output correlated double sampling circuits are also used to suppress fixed-pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352/spl times/288 (CIF) has been designed and fabricated by using 0.25-/spl mu/m single-poly-five-level-metal (1P5M) N-well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 47.29 /spl mu/m/sup -2/. The fabricated OPAPS CMOS imager has a pixel size of 8.2/spl times/.2 /spl mu/m, fill factor of 42%, and chip size of 3630/spl times/3390 /spl mu/m. Moreover, the measured maximum frame rate is 30 frames/s and the dark current is 82 pA/cm/sup 2/. Additionally, the measured optical dynamic range is 65 dB. It is found that the proposed OPAPS structure has lower dark current and higher optical dynamic range as compared with the active pixel sensor (APS) and the conventional passive pixel sensor (PPS). Thus, the proposed OPAPS structure has high potential for the applications of high-quality and large-array-size CMOS imagers.     

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

A high fill-factor self-buffered active pixel sensor and a tunable injection current compensation architecture for high dynamic range imager are proposed for scaled standard CMOS technology. The new cell, including a photo diode formed by n-well and p-type substrate and an one-transistor output buffer, shows enhanced characteristics in output voltage swing and sensitivity compared with conventional APS. The imager can achieve fill-factor of 55%, sensitivity of 3.4 V/sec-lux, and large output swing of 2.2 V at V/sub DD/=3.3 V for 0.25-/spl mu/m CMOS technology. In addition, the proposed tunable injection current compensation architecture can improve dynamic range by as much as 40 dB and can be tailor designed to meet various application specifications. A dynamic range of up to 120 dB is projected by simulation results. Experimental results of the new structure, as well as simulated design of the circuit, are presented.     

A dual pixel-type array for imaging and motion centroid localization

An imager chip has been designed, fabricated, and tested having two unique pixel types interleaved on the same array. The dual-pixel design enables optimization for two separate tasks. One type of pixel is an active pixel sensor (APS), which is used to produce a low-noise image. The other type is a custom-designed pixel optimized for computing the centroid of a moving object in the scene. The APS array is 120 columns /spl times/36 rows, with a pixel size of 14.7/spl times/14.7 /spl mu/m. The centroid array has 60 columns and 36 rows, with a larger pixel size of 29.4/spl times/29.4 /spl mu/m. The chip was fabricated using standard scalable rules on a 0.5 /spl mu/m 1P3M CMOS process. APS images were taken at a frame rate of 30 fps-8300 fps and centroid data was taken at a rate of 180-3580 (x,y) coordinates per second. The chip consumed 2.6 mW.     

A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed-pattern noise reduction

A novel logarithmic response CMOS image sensor fabricated by 0.25-/spl mu/m CMOS logic process is proposed. The new cell has an output voltage swing of 1 V in the targeted illumination range, which makes it less susceptible to noises in the readout system. Furthermore, the proposed new cell with in-pixel CDS control drastically reduces the fixed pattern noise in logarithmic mode CMOS APS. Comparing with a conventional pixel, a reduction of 10 times in fixed-pattern noise is demonstrated in the new logarithmic response CMOS image sensor.     

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.     

A CMOS smart pixel for active 3-D vision applications

A CMOS smart pixel aimed at three-dimensional vision applications is introduced. It is suitable for scannerless laser ranging systems which employ the indirect time-of-flight measuring technique to recover distance information. The pixel is operated with trains of light pulses generated by an external source to illuminate the scene and contains most of the processing electronics to perform signal accumulation and noise reduction operations. The smart pixel architecture includes an N-well photodiode plus a self-biasing voltage amplifier and a switched-capacitor fully differential stage. The pixel is fabricated in standard CMOS 0.6 /spl mu/m technology and measures 180/spl times/160 /spl mu/m/sup 2/ (including the photodiode) with a fill factor of 14%. Electrooptical test results confirm the smart pixel functionality in a range of distance from 3 m to 9 m, and the accuracy achieved for preliminary distance measurements is 15 cm. Both the accuracy and the extension of the range of distance are supposed to be improved by reducing setup and environmental noise contributions that limit the pixel performance.     

Microelectronic capacitance transducer for particle detection

This paper describes the CMOS circuit design of a sensor for detecting changes of capacitance due, for instance, to the incidence of particles or bubbles on the electrodes. The circuit is based on a simple design originating at the University of California, Berkeley, for measuring crosstalk on integrated circuits. The basic front-end sensor circuit comprises eight MOSFETs and has a sensitivity of 40 mV/fF. A differential amplifier receives the outputs from two sensor circuits each having 20-/spl mu/m square inter-digitated electrodes. The resulting sensitivity of the fabricated sensor is 1 V/fF with a noise level equivalent to 10 aF. Monte Carlo circuit simulations have been used to identify transistor dimensions to yield acceptable yield, and prototype custom silicon chips have been fabricated using a 0.8-/spl mu/m CMOS process. Static and dynamic tests, using polyamide particles as small as 10-/spl mu/m diameter, verify correct operation of the sensors. The sensor is now being developed for application in miniature electrical tomography systems.     

A CMOS focal-plane motion sensor with BJT-based retinal smoothing network and modified correlation-based algorithm

This work presents and implements a CMOS real-time focal-plane motion sensor intended to detect the global motion, using the bipolar junction transistor (BJT)-based retinal smoothing network and the modified correlation-based algorithm. In the proposed design, the BJT-based retinal photoreceptor and smoothing network are adopted to acquire images and enhance the contrast of an image while the modified correlation-based algorithm is used in signal processing to determine the velocity and direction of the incident image. The deviations of the calculated velocity and direction for different image patterns are greatly reduced by averaging the correlated output over 16 frame-sampling periods. The proposed motion sensor includes a 32/spl times/32 pixel array with a pixel size of 100/spl times/100 /spl mu/m/sup 2/. The fill factor is 11.6% and the total chip area is 4200/spl times/4000 /spl mu/m/sup 2/. The DC power consumption is 120 mW at 5 V in the dark. Experimental results have successfully confirmed that the proposed motion sensor can work with different incident images and detect a velocity between 1 pixel/s and 140,000 pixels/s via controlling the frame-sampling period. The minimum detectable displacement in a frame-sampling period is 5 /spl mu/m. Consequently, the proposed high-performance new motion sensor can be applied to many real-time motion detection systems.     

CMOS magnetic field to frequency converter

In this paper, a CMOS magnetic field to frequency converter with high resolution is presented. It is composed of two voltage-controlled ring oscillators whose output frequency differences linearly vary with the magnetic field perpendicular to the chip surface. The prototype circuit has been fabricated in a 0.5-/spl mu/m CMOS process and operated at a 5-V supply voltage. The measured sensitivity is 24 kHz/mT and the power consumption is 5.1 mW. The small equivalent resolution of at least 20 /spl mu/T can be achieved. The frequency offset is 42 kHz when no magnetic field applied. Its nonlinearity within /spl plusmn/120 mT is smaller than 0.56%.     

220-MHz monolithically integrated optical sensor with large-area integrated PIN photodiode

We propose a PIN photodiode integrated in a BiCMOS process which combines a quantum efficiency of nearly 100% for red light, fast response times, and a low junction capacitance. Bandwidths of 720 MHz at 660 nm and 683 MHz at 850 nm are achieved for this PIN photodiode. It allows the design of fast optoelectronic integrated circuits for many advanced applications in optical sensing, optical storage systems, and optical data transmission for optical wavelengths ranging at least from 660 to 850 nm. Because of the low photodiode capacitance of 0.01 fF//spl mu/m/sup 2/, it is possible to achieve high bandwidths, even with large photodetector areas. The proposed optical receiver employing a PIN photodiode with a diameter of 500 /spl mu/m and a capacitance of only 2.2 pF attains a -3-dB bandwidth of 220 MHz, which corresponds to a maximum nonreturn-to-zero data rate of 300 Mbit/s.     

A low-photocurrent CMOS retinal focal-plane sensor with a pseudo-BJT smoothing network and an adaptive current Schmitt trigger for scanner applications

In this work, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt trigger is proposed. The proposed structure is very simple and compact. This new circuit can easily be implemented in CMOS technology with a small chip area. Another innovation of this circuit is that the proposed circuit could be operated for low-induced current levels (pA), and the current hysteresis of the proposed current Schmitt trigger could be adjusted adaptively according to the value of induced photocurrents. In this work, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes a 32 /spl times/ 32 pixel array with a pixel size of 70 /spl times/ 70 /spl mu/m/sup 2/. The fill factor is 75% and the total chip area is 3000 /spl times/ 3030 /spl mu/m/sup 2/. It is with fully functional 32 /spl times/ 32 implementations consuming less than 8.8 /spl mu/W per pixel at 3.3 V. Measurement results show that the proposed new retinal focal-plane sensor has successfully been used in character recognition of scanner systems, such as pen scanners, etc.     

CMOS pixels for subretinal implantable prothesis

This work reports on the design, fabrication, and characterization of CMOS pixels for subretinal implants, which seems to be an effective way to recover visual capabilities in some types of blindness. Two possible approaches are presented for CMOS pixel implementation: 1) an approach based on a light-controlled oscillator (LICOS) using a ring oscillator with an odd number of inverters and 2) an approach based on distributing a square signal at each pixel that filters out a number of pulses depending of the light intensity wave across the chip (WATCH). Both types of pixels fabricated in 0.35-/spl mu/m CMOS demonstrate good mimic of the electrical behavior of human retina, with low-power consumption (typically 1 mW for a 14/spl times/14 matrix of pixels) and having small dimensions (75/spl times/78.5 /spl mu/m/sup 2/ for LICOS and 70/spl times/50 /spl mu/m/sup 2/ for WATCH), which make them suitable for practical implants. Experimental validation is reported on physiological solutions. Because of its characteristic, the proposed matrix of pixels could be considered as one of the first stand-alone highly integrated solutions for subretinal implant chips.     

A versatile built-in CMOS sensing device for digital circuit parametric test

A versatile CMOS current sensing device is proposed as a built-in self-test (BIST) monitor for conventional digital I/sub DDQ/ power supply current test. A novel sensor topology is successfully employed in a current monitoring testing scheme. The sensor is implemented in two CMOS processes, 0.13 /spl mu/m and 0.18 /spl mu/m with 1.2-V and 1.8-V power supply, respectively. For verification purposes, performances of the 0.13-/spl mu/m design are investigated on several types of digital circuits: 64-bit RCA adder, 16-bit register, and inverter chain. Our analysis shows excellent detection capabilities of noncatastrophic short and open defects. Overall performance penalty and power supply degradation of the circuit under test are evaluated on 1.2-V 500-gate, 1000-gate, and 2000-gate asynchronous digital logic. Average power supply degradation of the 2000-gate logic tested at 20 MHz is recorded to be less than 0.6% which produced a 250-ps delay in the 100-gate critical path. The presented sensor is a scalable and practical embedded solution for high-frequency parametric I/sub DDQ/ test of standard CMOS digital circuits.     

Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators

In this paper, two magnetic-to-digital converters (MDCs) using single-amplifier-based second-order delta-sigma modulators (DSMs) are presented to detect the dc magnetic field. The proposed second-order DSM required only a single-operational amplifier to achieve the second-order noise shaping. Both the proposed circuits have been fabricated in a 0.5-/spl mu/m CMOS DPDM process, and the resolution of 11 bits can be achieved. The measured sensitivities are 1.486 and 0.459 mV/mT, and the minimum detectable magnetic fields are 0.6 mT and 0.4 mT for the MDC with and without the pre-amplifier, respectively. Both the measured nonlinearities are smaller than 1.3% within the range of /spl plusmn/ 100 mT.     

The enhancement of Q factor for patterned ground shield inductors at high temperatures

We report on an effective way of using a patterned ground shield (PGS) to enhance the Q factor of on-chip spiral inductors. We fabricated PGS inductors using both 0.18 /spl mu/m and 0.35 /spl mu/m CMOS processes, with M1 and poly strip PGSs, respectively. The strip width and spacing of the PGSs are W/sub g/=0.8 /spl mu/m and S/sub g/=0.45 /spl mu/m, with metal thicknesses of t/sub p/={0.54,0.2} /spl mu/m in the 0.18 /spl mu/m process, and t/sub p/={0.6,0.3} /spl mu/m in the 0.35 /spl mu/m process. The separation distance D between PGS and top metal layer is different in both processes. We found that the Q factor degradation of inductors at high temperatures can be effectively compensated by using PGS. Among all geometric parameters of a PGS in the 0.18 /spl mu/m process, the parameter D is the critical factor for the shielding effectiveness, and M1 PGS is much more efficient than poly strip PGS in improving the inductor performance over the temperature range of 298 K to 358 K. However, in the 0.35 /spl mu/m process the latter is better than the former.     

Fabrication, characterization, and analysis of a DRIE CMOS-MEMS gyroscope

A gyroscope with a measured noise floor of 0.02/spl deg//s/Hz/sup 1/2/ at 5 Hz is fabricated by post-CMOS micromachining that uses interconnect metal layers to mask the structural etch steps. The 1 /spl times/ 1 mm lateral-axis angular rate sensor employs in-plane vibration and out-of-plane Coriolis acceleration detection with on-chip CMOS circuitry. The resultant device incorporates a combination of 1.8-/spl mu/m-thick thin-film structures for springs with out-of-plane compliance and 60-/spl mu/m-thick bulk silicon structures defined by deep reactive-ion etching for the proof mass and springs with out-of-plane stiffness. The microstructure is flat and avoids excessive curling, which exists in prior thin-film CMOS-microelectromechanical systems gyroscopes. Complete etch removal of selective silicon regions provides electrical isolation of bulk silicon to obtain individually controllable comb fingers. Direct motion coupling is observed and analyzed.     

Development and comparative analysis of fluxgate magnetic sensor structures in PCB technology

In this paper, we present a family of fluxgate magnetic sensors on printed circuit boards (PCBs), suitable for an electronic compass. This fabrication process is simple and inexpensive and uses commercially available thin ferromagnetic materials. We developed and analyzed the prototype sensors with software tools based on the finite-element method. We developed both singleand double-axis planar fluxgate magnetic sensors as well as front-end circuitry based on second-harmonic detection. Two amorphous magnetic materials, Vitrovac 6025X (25 /spl mu/m thick) and Vitrovac 6025Z (20 /spl mu/m thick), were used as the ferromagnetic core. We found that the same structures can be made with Metglas ferromagnetic core. The double-axis fluxgate magnetic sensor has a sensitivity of about 1.25 mV//spl mu/T with a linearity error of 1.5% full scale, which is suitable for detecting Earth's magnetic field (/spl plusmn/60 /spl mu/T full-scale) in an electronic compass.     

Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

We proposed "reverse-order source/drain formation with double offset spacer" (RODOS) structure for low-power and high-speed applications. Both simulation and experimental data were used to evaluate the potential of the structure. It showed improved performance in terms of poly-depletion effect, dc characteristics, gate delay (CV/I), switching energy (CV/sup 2/) and linearity (V/sub IP3/). It satisfied all the requirements of LOP and LSTP for 90 nm technology node in ITRS 2002. Simulation predicted 794 /spl mu/A//spl mu/m in on-current, 0.1 nA//spl mu/m in off-current, 65 mV/V in DIBL, 80 mV/dec in SS, 1.29 ps in gate delay, 198 GHz in f/sub T/ and 0.151 fJ in switching energy in addition to enhanced linearity. Finally, we confirmed the high feasibility and potential of the RODOS MOSFET's for low-power and high-speed applications such as an LNA in portable communication appliances.     

Highly sensitive PtSi/porous Si Schottky detectors

Presents the first experimental results on PtSi/porous Si Schottky detectors. Si pores have been filled by Pt through electrodeposition. Under proper temperature treatment, Pt reacts with Si creating a PtSi layer that uniformly covers the walls of the pores. The excess unreacted Pt inside the pores is etched away leaving empty spaces behind. The spectral response of such a detector is very wide, covering from 0.9 up to at least 7 /spl mu/m of IR radiation in back illumination mode. Excellent responsivities, such as 60 A/W at 1 /spl mu/m and 0.96 A/W at 4 /spl mu/m of IR radiation is exhibited. Reverse bias current-voltage characteristics exhibit a breakdown type behavior with a breakdown voltage at about 10 V. The general shape of the reverse bias I-V curve, the wide spectral range, and high responsivity are explained through tunneling and avalanche multiplication. It is proposed that large fringing fields developed at sharp edges of the porous surface cause tunneling and avalanche multiplication.     

Theoretical approach to CMOS APS PSF and MTF modeling - evaluation

In this work, a fully theoretical CMOS active pixel sensor (APS) modulation transfer function model is formulated, evaluated, and compared with practical results. The model is based on a two-dimensional diffusion equation solution and covers the symmetrical photocarriers diffusion effect together with the impact of the pixel active area geometrical shape. Thorough scanning results obtained by means of a unique submicron scanning system (the S-cube system) from various APS chips, implemented in a standard CMOS 0.35-/spl mu/m technology, are compared with our theoretical predictions. The agreement of the presented comparison results indicates that for any potential active area shape, an analytical reliable estimate of image performance is possible.