Dual-period self-refresh scheme for low-power DRAM's with on-chipPROM mode register

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAM's is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

A circuit technology for a self-refresh 16 Mb DRAM with less than0.5 μA/MB data-retention current

A 16M self-refresh DRAM achieving less than 0.5 μA per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a V_BB pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 μA per megabyte. Furthermore, the addition of a gate-received V_BB detector (GRD) reduces dc retention current to less than 0.1 μA per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery     

A 4K/spl times/8 dynamic RAM with self-refresh

A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, counter and multiplexer. A high-speed arbiter resolves simultaneous memory and refresh requests. Redundant rows are used for increased manufacturing yields. Polysilicon fuses are electrically programmed to select redundant rows.     

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.     

Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.     

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm² with under 1 μW power consumption for providing 0.7 °C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.     

Sub-1-μA dynamic reference voltage generator forbattery-operated DRAMs

A new reference voltage generator with ultralow standby current of less than 1 μA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-μm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/°C from room temperature to 100°C, and output noise of less than 12 mV for 1 V_p-p V_cc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAMs with low active and data-retention currents comparable to SRAMs     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Strain-compensated InGaAsSb multiple quantum-wells with digital AlGaAsSb barriers for midinfrared lasers

Midinfrared InGaAsSb-AlGaAsSb strain-compensated multiple quantum-wells (SCMQW) have been grown by solid-source molecular beam epitaxy. Short-period (AlGaAsSb)/sub y/--(AlGaSb)/sub 1-y/ digital barriers were employed to avoid growth interruptions at the barrier-well interfaces, thereby significantly improving the structural and optical properties of the InGaAsSb SCMQW as evidenced by X-ray diffraction and photoluminescence measurements. Based on these high-quality SCMQW, a room-temperature threshold current density as low as 163 A/cm/sup 2/ was achieved for 1000-/spl mu/m-long broad-area lasers emitting at 2.38 /spl mu/m in pulsed mode. The 880-/spl mu/m-long lasers retained a high characteristic temperature (T/sub 0/) of 165 K up to 80/spl deg/C and could operate at temperatures above 100/spl deg/C. A typical wavelength blueshift of 38 meV was observed in the SCMQW laser samples compared to the SCMQW-only samples.     

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells     

A low-noise folded bit-line sensing architecture for multigigabitDRAM with ultrahigh-density 6F2 cell [CMOS design]

The 6F² cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F² DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F² cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F² cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed     

Low threshold and high uniformity for novel 1.3-/spl mu/m-strained InGaAsP MQW DC-PBH LDs fabricated by the all-selective MOVPE technique

1.3-/spl mu/m-strained InGaAsP multiquantum-well (MQW) double-channel planar buried heterostructure laser diodes (DC-PBH-LDs) were fabricated by all-selective metalorganic vapor phase epitaxy (MOVPE). In the fabrication process, the strained MQW active layer and current-blocking structures were directly formed by selective MOVPE without a semiconductor etching process. A low-threshold current (I/sub th/=2.6 mA@25/spl deg/C for 200-/spl mu/m-long 70%-90% facets) and excellent high-temperature operation (T/sub 0/=84 K, 25/spl deg/C-60/spl deg/C and T/sub 0/=70 K, 25/spl deg/C-85/spl deg/C) were achieved. Furthermore, extremely uniform threshold current and slope efficiency were observed, The median time to failure for these LDs was estimated to be more than 100000 h under the 85/spl deg/C-5 mW aging condition.     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference scheme

We present a microcontroller having a 0.5-/spl mu/A standby current on-chip regulator. To break through the area overhead problem which a conventional regulator scheme suffers from to achieve small standby current, we propose a dual-reference scheme in which one voltage reference circuit is provided for active mode and another voltage reference circuit is provided for standby mode. For the voltage reference circuit for standby mode, a resistor-free circuit was used to achieve small current consumption without occupying large area. The microcontroller was fabricated in a 0.18-/spl mu/m CMOS process. The implementation and measurement results show that the dual-reference scheme achieves 0.5-/spl mu/A current consumption of the regulator in standby mode with 50% smaller area than the conventional scheme. The measured standby current of the whole chip was 2.0 /spl mu/A.     

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.     

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

In this letter, we analyze the effects of temperature (from -50/spl deg/C to 200/spl deg/C) and substrate impedance on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF/sub min/) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum Q-factor (Q/sub max/), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency (f/sub SR/) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and Q-factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance (R/sub s/), the parallel substrate resistances (R/sub sub1/ and R/sub sub2/), and the resistance R/sub s1/ of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.     

Highly reliable and high-yield 1300-nm InGaAlAs directly modulated ridge fabry-Perot lasers, operating at 10-gb/s, up to 110/spl deg/C, with constant current swing

Transceivers for 300-m multimode links, based on a serial 10-Gb/s laser source and incorporating a receiver based on electronic dispersion compensation (EDC), are creating the first high-volume application for a 10-Gb Fabry-Perot (FP). A highly reliable and high-yield uncooled ridge FP laser is presented. The device shows excellent power characteristics in the 25/spl divide/150/spl deg/C temperature range with very high T/sub 0/ (95 K in the temperature range 0/spl divide/85/spl deg/C and still 78 K at 150/spl deg/C). Outstanding dynamic performances are also shown: 6 dB of extinction ratio can be achieved up to 110/spl deg/C by using a constant current swing of 50 mA. Because of their enhanced performances, these devices have enabled single temperature setting of the optical module, leading to a significant test cost reduction.