24位高精度模数转换器ADS1258的原理及应用

介绍了16通道、低功耗、高精度A/D转换器ADS1258的性能特点、引脚功能和内部结构,给出了ADS1258与C8051F120之间通过SPI通信的接口硬件电路设计,提出了在实际电路设计中应注意的问题.     

基于DSP和CPLD的低功耗多路数据处理系统设计

本文介绍了一种基于DSP和CPLD的低功耗多路数据采集处理系统。整个系统由DSP和CPLD动态地设置A/D采样通道,控制6路16位高精度A/D转换器ADS7805的启动和停止。由DSP对采样数据进行读取和处理。     

基于ADS1274的可控式高精度数据采集系统设计

针对传统便携式振动测试仪测量精度低,动态范围小,功耗大等缺点,采用24位高精度∑-△型A/D转换器ADS1274和数字信号处理器TMS320VC5502构建了一个模式可控的高精度数据采集系统.该系统可实现24位精度、4通道同步数据采集,最高采样频率可这128 KS/s,并能动态控制A/D转换器的工作模式.实验结果表明,该系统设计既具有低功耗、高精度和宽动态范围等优点,又具有良好的应用前景.     

ADS7864在电网数据采集中的应用

介绍了一种高速，低功耗，6通道双12位A／D转换器ADS7864及其用在电网数据采集中的应用。     

THS5641A 8位100MSPS Comms DACTMD/A转换器

THS5641A是一种专门为视频应用与在有线和无线通信系统中数字数据传输应用而优化设计的8位分辨率D/A转换器.这种8位D/A转换器是Comms DACTM系列高速低功耗CMOS D/A转换器产品的一员.Comms DACTM系列包括引脚兼容的14/12/10/8位D/A转换器.所有器件提供相同的接口选择、小型外廓封装和引脚排列;THS5641A提供优异的AC和DC性能,同时支持高达100MSPS的校正速率.     

ADS7812及其在智能型互感器校验仪中的应用

文章介绍了一种性能优越的串行数据接口 12位A/D转换器———ADS7812的基本结构、性能及其在智能型互感器校验仪中的应用方法。     

基于嵌入式Linux的A／D转换设备驱动设计

为了满足高精度、高速度的A/D转换应用需求,可以在嵌入式Linux系统中使用ADS7844作为A/D转换器.简述了12位串行A/D转换器ADs7844的结构和工作原理,并且以S3C2410为例介绍嵌入式微处理器外接A/D转换器(ADs7844)硬件电路及其在Linux2.6内核中驱动程序的设计.结果表明ADS7844设备驱动能很好地实现数据采集,并且具有很高的稳定性,ADS7844进行A/D转换速度非常快,精度也很高,达到了设计要求.     

基于A/D转换器ADS7813的信号采集系统设计

介绍了一种串行16位A/D转换器ADS7813的主要特性、使用方法,以及它与单片机组成的多路模拟信号采集系统,最后提出了ADS7813应用中应注意的问题。     

12位A/D转换器ADS7864在电网谐波分析仪中的应用

ADS7864是Burr-Brown公司开发的12位6通道A/D转换器,介绍了ADS7864的工作原理、内部结构、工作模式及编程要点,给出了ADS7864在电网谐波分析仪中与数字信号处理器TMS320F206的接口应用实例,并且对DSP与A/D转换器的接口特点进行了总结.     

低功耗串行12位A／D转换器的应用

Burr-Brown公司的 ADS7812是一种低功耗、单+5V电源、串行 12位逐步逼近的A/D转换器。其应用范围包括:数据采集系统,工业控制,测试设备,数字信号处理等。ADS7812电路构成见图1。 在此简介其中的一些应用电路。QSPI接口 QSPI(排队串行外设接口)是微控制器配备的一种接口。ADS7812与QSPI之间的一个简单接口示于图2。此接口假定变换脉冲不是来自微控制器,而ADS7812是唯一串行外设。     

基于DSP的16通道声发射同步数据采集电路设计

针对煤岩声发射信号监测系统的需求,采用16位定点DSP芯片TMS320VC5509A和高精度A/D转换器ADS1278设计了一种具有24位分辨率、16通道同步数据采集功能的数据采集电路。控制接口采用I2C接口扩展I/O的方式实现,数据接口采用McBSP接口以帧同步方式实现,2片ADS1278采用菊花链的方式级联。给出了硬件电路、底层软件和测试结果,该数据采集电路具有接口简单、高性能、低功耗、设置灵活等特点,已经应用于课题组研制的煤岩声发射监测系统中。     

ADS8344及其在电子式互感器高压侧数据处理系统中的应用

电子式互感器是一种利用现代数字处理和光纤通信技术来实现电力系统电压、电流测量和保护的新型互感器装置。ADS8344是TI公司生产的8通道、16位、高精度、低功耗A／D转换芯片。TMS320LC545是TI公司生产的16位、低功耗、高速DSP芯片。文中介绍了ADS8344的主要特点，给出了其在电子式互感器高压侧数据处理系统中与TMS320LC545的接口设计。     

串行A/D转换器ADS1110及其在AT89C51单片机中的应用

针对51单片机系统中常用的A/D转换器价格高、精度低的缺点.介绍TI公司的16位的带有I2C串行接口的A/D转换器ADS1110的工作原理,给出ADS1110与AT89C51单片机系统的接口电路和软件设计.实践证明,ADS1110具有高性价比和实用性.     

新型16位ADS7811与TMS320F206的接口电路

ADS7811是一种新型的 16位的模数转换器 ,它自带采样保持器 ,最高采样频率可达2 5 0kHz ,转换结果采用 16位并行输出 ,速度极快。TMS32 0F2 0 6是数字信号处理器中的一种 ,自带 32kE2 PROM。文中介绍了ADS7811的功能和它与数字信号处理机的接口电路以及软件设计方法。     

ADS7844在低功耗数据采集系统中的应用

详细介绍了12位串行模数转换器ADS7844的结构及工作原理 ,给出了一个实用的低功耗数据采集系统的设计方案 ,同时给出了相关的硬件电路和软件程序。     

AMULET2e: an asynchronous embedded controller

AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks     

High-performance low-power CMOS memories using silicon-on-sapphire technology

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.     

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.     

A 10000 frames/s CMOS digital pixel sensor

A 352×288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-μm CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4×9.4 μm with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 μV/e^-. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization