基于ARM+FPGA的影像交互与显示系统设计

为促进航空测绘信息获取的数字化、一体化、实时化,本文利用FPGA(Field-Programmable Gate Array,即现场可编程门阵列)并行处理的优势结合ARM处理器低功耗高性能的特点,基于ARM+FPGA的双核硬件架构实现了影像的交互与显示。该系统以Linux操作系统为软件开发平台,以ARM11嵌入式处理器为硬件核心、FPGA作为协处理器,采用FPGA片内FIFO(First Input First Output,即先进先出存储器)作为ARM处理器与FPGA之间的高速通信桥梁,针对Linux 2.6.36内核完成了对FPGA设备的驱动设计,并基于Qt图形用户界面实现了影像的实时显示。测试结果表明,ARM处理器与FPGA之间能够实现VGA(640×480)图像的高速交互,帧率可达26帧/s,最大传输带宽为182Mbps。该系统不仅体积小、功耗低、成本低,而且稳定性好、功能强,能够满足航空遥感摄影系统的实时性要求。     

Design Methodology for Offloading Software Executions to FPGA

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.     

SoC based floating point implementation of differential evolution algorithm using FPGA

This paper presents floating point design and implementation of System on Chip (SoC) based Differential Evolution (DE) algorithm using Xilinx Virtex-5 Field Programmable Gate Array (FPGA). The hardware implementation is carried out to enhance the execution speed of the embedded applications. Intellectual Property (IP) of DE algorithm is developed and interfaced with the 32-bit PowerPC 440 processor using processor local bus (PLB) of Xilinx Virtex-5 FPGA. In the proposed architecture the algorithmic parameters of DE are scalable. The software and hardware implementation of the DE algorithm is carried out in PowerPC embedded processor and hardware IP respectively. The optimization of numerical benchmark functions and system identification in control systems are implemented to verify the proposed hardware SoC platform. The performance of the IP is measured in terms of acceleration gain of the DE algorithm. The optimization problems are solved by using floating point arithmetic in both embedded processor and hardware. The experimental result concludes that the hardware DE IP accelerates the execution speed approximately by 200 times compared to equivalent software implementation of DE algorithm on PowerPC 440 processor. Further, as a case study an Infinite Impulse Response (IIR) based system identification task on SoC using the developed hardware accelerator is implemented.     

Hardware/Software Communication and System Integration for Embedded Architectures

Embedded system architectures comprising of software programmable components (e.g. DSP, ASIP, and micro-controller cores) and customized hardware co-processors, integrated into a single cost-efficient VLSI chip, are emerging as a key solution to todays microelectronics design problems. This trend is being driven by new emerging applications in the areas of wireless communication, high-speed optical networking, and multimedia computing, fueled by increasing levels of integration. These applications are often subject to stringent requirements in terms of processing performance, power dissipation, and flexibility. A key problem confronted by embedded system designers today is the rapid prototyping of an application-specific embedded system architecture where different combinations of programmable processor components, library hardware components, and customized hardware components must be integrated together, while ensuring that the hardware and software parts communicate correctly. Designers often spend an enormous time on this highly error proned task. In this paper, we present a solution to this embedded architecture co-synthesis and system integration problem based on an orchestrated combination of architectural strategies, parameterized libraries, and software CAD tools.     

基于Nios软核处理器的嵌入式系统设计

利用软核处理器构造嵌人式系统的突出优点就是可编程性、可裁减性、易操作性、灵活性以及低成本,这些特点都使得软核处理器具有很强的竞争力。Nios软核处理器集成在FPGA芯片内部,是目前最流行的软核处理器之一,本文给出了基于Nios软核处理器的嵌入式系统的设计方法。文章研究了Nios软核处理器的结构和特点,提出了系统硬件平台的设计方案,讨论了系统的SOPC集成设计,分析了系统的软件设计方法,总结了系统的启动流程,给出了系统的测试结果。实践证明,该嵌入式系统功能完整、集成度高、稳定可靠、简洁实用,具有可编程性、可裁减性、易操作性、灵活性以及低成本等特点,具有广泛的应用价值。     

基于TMS320DM368的高清视频采集系统设计与实现

实现了基于TMS320DM368嵌入式处理器的高清视频采集系统,详细介绍了系统的总体架构及主要的软硬件模块。首先,分析了核心处理模块性能及硬件采集模块功能;其次,描述了高清视频采集、处理及传输等模块的软件实现流程,给出了在嵌入式Linux平台下基于Web服务器移植的实现过程;最后,对系统进行测试,结果表明本系统达到了预期的高清视频采集及传输功能,图像清晰度高,实时性好,可以很方便地应用在需要高清视频监视的场合。     

基于片上系统的电磁频谱监测接收机设计

探讨一种适合组建网格化电磁频谱监测系统的接收机设计技术,提出基于Xilinx公司最新的高性能Zynq-7000系列嵌入式处理器平台的接收机设计方案,研究了Zynq-7000系列异构FPGA器件的特点及开发流程,给出了基于Zynq-7000片上系统的频谱监测接收机软、硬件设计细节,重点研究在Zynq-7000嵌入式处理器平台下高速FFT频谱分析、大容量监测数据存储以及精密时间同步的实现方法。     

Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs

This paper presents a novel architecture combining an application specific instruction set processor (ASIP) core and an application domain specific embedded FPGAs (eFPGAs) used as flexible accelerator for the ASIP. The eFPGA is based on a parametrisable architecture template optimised for arithmetic oriented applications. It was designed as a physically optimised VLSI-macro using a flexible design methodology also sketched in this paper. Quantitative comparisons of the eFPGA with a commercial standard FPGA show significant improvements in energy, area and timing delays. Simulations of the new ASIP-eFPGA architecture have been conducted using a model based approach to evaluate its efficiency. The results show that power- and area-efficiencies similar to an FPGA can be achieved for the flexible ASIP-eFPGA while preserving the flexibility of a software programmable processor.     

基于OpenRISC1200的孤立词识别系统设计与实现

介绍了一个基于32位OpenRISC1200开放源码微处理器内核的小词汇量孤立词语音识别系统结构。根据软硬件协同设计方法，研究和比较了孤立词语音识别各个环节的计算量，合理分配软硬件资源，并提出一种适合FPGA（现场可编程门阵列）实现的动态时间规正硬件实现思路，大大缩短识别响应时间。该系统在成本和知识产权方面都较市场上流行的ARM、8051等内核有优势。实验结果表明，在特定场合下，该系统对于100个词组的平均识别响应时间少于2s，特定人识别率95％以上，非特定人识别率87％以上。     

Reconfigurable pipelined 2-D convolvers for fast digital signalprocessing

In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated. However, the proposed concept is not limited to a particular processor     

基于NIOSII软核的嵌入式信令处理系统实现

文章介绍嵌入式通信信令处理系统的设计,充分利用了NiosII软核特性,基于SOPC设计思想,在一块FPGA芯片内实现一个相对独立的信令处理系统。并结合整个系统的开发过程,介绍此类系统硬件、软件的设计方法和流程。     

The design and implementation of the IEEE 802.11 MAC based on soft-core processor and RTOS

The implementation method of the IEEE 802.11 Medium Access Control （MAC） protocol is mainly based on DSP （Digital Signal Processor）/ARM （Advanced Reduced instruction set computer Machine） processor or DSP/ARM IP （Intellectual Property） core. This paper presents a method based on Nios II soft-core processor embedded in Altera＇s Cyclone FPGA （Field Programmable Gate Array） and MicroC/OS-II RTOS （Real-Time Operation System）. The benefits and drawbacks of above methods are compared, and then the method presented in this paper is described. The hardware and software partitioning are discussed; the hardware architecture is also illustrated and the MAC software programming is described in detail. The presented method has some advantages, such as low cost, easy-implementation and very suitable for the implementation of IEEE 802.11 MAC in research stage.     

The Design and Implementation of Embedded Security CPU Based on Multi-strategy

Control flow monitoring,information flow tracking and memory monitoring are the three main solutions to enhance the security of embedded system at the hardware architecture level.However,most of the current studies about the security of embedded system consider the above solutions in separate dimensions rather than a combined effort.We start from the operation model at the instruction level,and propose a security multi-strategy which combines information flow tracking and memory monitoring by studying the security operating mechanism of embedded system.As a hardware approach this strategy extends the embedded processor architecture with additional security defense control.The experimental results show this multi-strategy is more effective and can detect more malicious attacks than a single solution.The effectiveness of our proposed security multi-strategy has been verified in a Field programmable gate array (FPGA) prototype platform based on a customized Leon3 microprocessor.     

基于ARM的嵌入式WEB服务器研究

在各种基于客户机／服务器模式的Internet应用中，为了降低服务器的功耗、体积和成本,提出了采用嵌入式WEB服务器代替传统的PC机服务器的方法。介绍了基于ARM嵌入式的WEB服务器设计，分析了系统的硬件配置与软件实现,探讨了嵌入式操作系统的选择和HTTP服务器的工作流程，并进行了相应的实验。     

Hardware-software co-design of embedded systems [and prolog]

This paper surveys the design of embedded computer systems, which use software running on programmable computers to implement system functions. Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design problem-the design of the hardware and software components influence each other. This paper emphasizes a historical approach to show the relationships between well-understood design problems and the as-yet unsolved problems in co-design. We describe the relationship between hardware and software architecture in the early stages of embedded system design. We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design. We also describe design and synthesis techniques for co-design and related problems     

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

Embedded system security is often compromised when "trusted" software is subverted to result in unintended behavior, such as leakage of sensitive data or execution of malicious code. Several countermeasures have been proposed in the literature to counteract these intrusions. A common underlying theme in most of them is to define security policies at the system level in an application-independent manner and check for security violations either statically or at run time. In this paper, we present a methodology that addresses this issue from a different perspective. It defines correct execution as synonymous with the way the program was intended to run and employs a dedicated hardware monitor to detect and prevent unintended program behavior. Specifically, we extract properties of an embedded program through static program analysis and use them as the bases for enforcing permissible program behavior at run time. The processor architecture is augmented with a hardware monitor that observes the program's dynamic execution trace, checks whether it falls within the allowed program behavior, and flags any deviations from expected behavior to trigger appropriate response mechanisms. We present properties that capture permissible program behavior at different levels of granularity, namely inter-procedural control flow, intra-procedural control flow, and instruction-stream integrity. We outline a systematic methodology to design application-specific hardware monitors for any given embedded program. Hardware implementations using a commercial design flow, and cycle-accurate performance simulations indicate that the proposed technique can thwart several common software and physical attacks, facilitating secure program execution with minimal overheads     

高速实时数据采集智能控制器的设计与实现

文章以嵌入式和数据采集技术为基础,研究设计并实现了基于ARM+FPGA体系架构面向高速实时数据采集应用的一种实用新型智能控制器。本文阐述了主处理器ARM最小系统、协处理器FPGA最小系统和ARM与FPGA通信接口等硬件系统技术的实现,以及Linux FPGA字符设备驱动程序开发、协处理器FPGA控制程序和主处理器ARM应用程序设计。智能控制器运用FPGA并行运算处理结构的优势,控制ADC进行高速数据采集。FPGA还可配置成软核处理器-Nios II嵌入式处理器,与ARM构成双核处理器系统。智能控制器通过ARM实现对FPGA的管理控制、实时数据采集和丰富外围接口的通信。