Electrical properties of high-quality ultrathin nitride/oxide stackdielectrics

The electrical properties of ultrathin nitride/oxide (N/O) stack dielectrics (2-4 nm), produced by in-situ jet vapor deposition (JVD), have been studied in some detail. Both theoretical calculation and experimental data show that the leakage current in the N/O stack is substantially lower than that in the single oxide layer of the same equivalent oxide thickness (EOT). When compared to the single nitride layer, the N/O stack yields a lower leakage current in the 3-nm thickness regime. In the 2-nm thickness regime, however, the leakage currents in the single nitride layer and the N/O stack are comparable. The tunneling current in the N/O stack depends not only on the thickness combination of the nitride and the oxide layers, but also on the injection polarity. Other important electrical properties of the N/O stack, including time-dependent-dielectric-breakdown (TDDB), stress-induced leakage current (SILC), carrier trapping, and interface characteristics are also reported. High quality field-effect transistors have been made of the N/O stack, and their properties will be reported     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Tunneling leakage current in oxynitride: dependence onoxygen/nitrogen content

It is widely known that the addition of nitrogen in silicon oxide, or the addition of oxygen in silicon nitride, affects its reliability as a gate dielectric. The authors examine the gate leakage current as a function of the oxygen and nitrogen contents in ultrathin silicon oxynitride films on Si substrates. It is shown that, provided that electron tunneling is the dominant current conduction mechanism, the gate leakage current in the direct tunneling regime increases monotonically with the oxygen content for a given equivalent oxide thickness (EOT), such that pure silicon nitride passes the least amount of current while pure silicon oxide is the leakiest     

To optimize electrical properties of the ultrathin (1.6 nm)nitride/oxide gate stacks with bottom oxide materials andpost-deposition treatment

The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH₃/N₂O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O₂-grown bottom oxide. In post-deposition treatment, increasing NH₃ nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N₂O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH₃ nitridation step     

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

Hole tunneling current through oxynitride/oxide stack and the stackoptimization for p-MOSFETs

A systematic study on hole-tunneling current through both oxynitride and oxynitride/oxide (N/O) stack is for the first time presented based on a physical model. The calculations are in good agreement with the available experimental data. With a given equivalent oxide thickness (EOT), and under typical operating gate voltages (|Vg|<2 V), hole-tunneling current (essentially the gate current) is found to be lowest through the oxynitride or N/O stack with ~33% of nitrogen (N). An optimized N/O stack structure with 33% (atomic percentage) nitrogen and with a 3 Å oxide layer for keeping acceptable channel interface quality is proposed to project the N/O gate dielectrics scaling limit using in MOSFETs     

恒压应力下超薄Si_3N_4/SiO_2叠层栅介质与SiO_2栅介质寿命比较

以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性.     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride（N/O）stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated，and ultra thin (＜2 nm＝ N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.     

超薄氮氧叠层栅介质的金属栅pMOS电容的电学特性

研究了高质量超薄氮化硅/氮氧化硅(N/O)叠层栅介质的金属栅pMOS电容的电学特性,制备了栅介质等效厚度小于2nm的N/O复合叠层栅介质,该栅介质具有很强的抗硼穿通能力和低的漏电流.实验表明这种N/O复合栅介质与优化溅射W/TiN金属栅相结合的技术具有良好的发展前景.     

超薄Si3N4/SiO2叠层栅介质可靠性研究

实验成功地制备出等效氧化层厚度为亚2nm的Nitride/Oxynitride(N/O)叠层栅介质难熔金属栅电极PMOS电容并对其进行了可靠性研究.实验结果表明相对于纯氧栅介质而言,N/O叠层栅介质具有更好的抗击穿特性,应力诱生漏电特性以及TDDB特性.进一步研究发现具有更薄EOT的难熔金属栅电极PMOS电容在TDDB特性以及寿命等方面均优于多晶硅栅电极的相应结构.     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

Investigation of Drain Disturb in SONOS Flash EEPROMs

The mechanism of drain disturb is studied in silicon-oxide-nitride-oxide-silicon Flash electrically erasable programmable read-only memory cells. It is shown that disturb is a serious problem in programmed cells and is caused by injection of hot holes from substrate into the oxide/nitride/oxide stack. The origin of these holes is identified by analyzing the influence of halo doping, channel doping, and channel length scaling on drain disturb. Band-to-band tunneling at the drain junction is normally the dominant source of these holes. It is also shown that holes generated out of impact ionization of channel electrons become dominant in cells with high channel leakage (especially at lower channel lengths). Finally, the effect of repeated program/erase cycling on drain disturb is studied. Drain disturb becomes less severe with cycling, the reasons for which are determined using gate-induced drain leakage measurements and device simulations     

Two silicon nitride technologies for post-SiO2 MOSFETgate dielectric

P-MOSFETs with 14 Å equivalent oxide thickness (EOT) were fabricated using both JVD Si₃N₄ and RTCVD Si₃ N₄/SiO_xN_y gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO₂ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.