软件无线电中的宽带射频前端

本文简要介绍了软件无线电的概念、特点和基本结构,着重分析了软件无线电技术对射频前端的性能要求,以及射频前端设计中的实际问题.     

软件无线电中的宽带射频前端

本文简要介绍了软件无线电的概念、特点和基本结构，着重分析了软件无线电技术对射频前端的性能 要求，以及射频前端设计中的实际问题。     

基于软件无线电跳频电台射频前端的研究

基于软件无线电的基本要求和发展趋势,提出了一种应用在软件无线电跳频电台中宽频段接收机的前端电路设计方案,分析了接收机射频前端二次混频方案结构的可行性,在对方案中各功能模块研究分析的基础上,完成了射频前端的滤波嚣、混频器、放大器等各模块的设计工作,并对整个系统进行了建模设计和仿真验证.仿真结果表明,接收机前端电路噪声系数...     

软件无线电中射频前端的设计

本文简要介绍了软件无线的概念、特点和基本结构，分析了软件无线电技术对射频前端的性能要求，着重阐述了具体设计宽带线性射频前端的技术难题和解决方案。     

基于软件无线电跳频电台射频前端的研究

基于软件无线电的基本要求和发展趋势,提出了一种应用在软件无线电跳频电台中宽频段接收机的前端电路设计方案,分析了接收机射频前端二次混频方案结构的可行性,在对方案中各功能模块研究分析的基础上,完成了射频前端的滤波器、混频器、放大器等各模块的设计工作,并对整个系统进行了建模设计和仿真验证。仿真结果表明,接收机前端电路噪声系数低,镜像抑制良好,增益合理,选择性合适,均满足设计要求。     

HF/VHF零中频接收机前端电路分析设计

以零中频接收机的射频前端在HF/VHF存在的问题为重点,深入研究零中频结构的射频前端结构,并通过电路设计提出解决方案,设计了基于软件无线电原理的HF、VHF双频段射频前端。通过模拟仿真,论证方案的可实现性以及所选器件能够满足设计方案的指标要求。     

一种软件无线电宽带射频前端的设计

比较了软件无线电宽带射频前端的几种技术方案特点及其可行性,提出了一种采用多路可配置信道组网射频前端方案,分析了其关键技术及解决措施;并以2～2 000 MHz宽带射频前端为例进行仿真,给出典型仿真结果,验证了方案的可行性.     

一种16通道软件无线电射频前端的设计与实现

随着无线通信技术的快速发展，MIMO技术得到了更加广泛的应用。而多通道射频前端是MIMO硬件系统中重要的组成部分，其性能指标对通信系统功能具有决定性影响。设计了一种16通道软件无线电射频前端，该设计结合集成收发器与超外差收发机架构的优势，可同时支持16路射频收发通道，具有调制精度高、动态范围大和体积小的特点。从实际射频测试结果看，该射频前端性能优异，工作频率10 MHz～6 GHz,最大信号带宽大于150 MHz,输入功率-40～27 dBm,输出功率-10～-110 dBm,差分误差矢量幅度小于0.37%,可适用于多通道软件无线电设备、信道仿真器等对射频指标和体积有要求的应用中。     

RFID发射前端的零中频电路设计

软件无线电技术增强了射频识别（RFID）系统的信号处理能力及兼容性,而零中频的设计思想进一步简化了射频前端结构。然而射频前端依然发挥着不可替代之重要功能,若在设计中将其地位置于软件子系统之下往往会恶化整体性能。本文对基于零中频技术的RFID射频发射前端进行了必要的理论分析,在此基础上,按照性能指标要求对系统进行了预增益仿真和谐波平衡仿真,以此作为模块选型和优化的依据,最后完成了射频前端设计。仿真结果表明,各项指标较为理想。     

软件无线电关键技术最新进展

1前言 近年来软件无线电技术研究取得了一些进展,但仍面临许多技术挑战,包括高速A/D、DSP数字处理、射频前端、天线技术等问题,可以说这些技术决定着软件无线电的发展和实现.     

An efficient integration of GPS and WCDMA radio front-ends

An efficient integration of global positioning system (GPS) and universal mobile telecommunication system (UMTS) radio front-end units is presented. The combined front-end unit includes the transmitter and receiver filters, duplex filter, power amplifier, buck regulator, and power detector for the UMTS wireless code-division multiple-access system. The GPS building blocks of the radio front-end unit consist of the low-noise amplifier and RF filter. The inter-system isolation was experimentally quantified and the compared against the minimum inter-system isolation requirements, defined according to desensitization and intermodulation tests in the GPS receiver. The characterized isolation of the antenna array provided 6 dB of margin over the minimum inter-system isolation requirements for 3-dB degradation of the carrier-to-noise ratio in GPS receivers. The UMTS portion of the radio front-end unit was verified against the Third-Generation Partnership Project standard.     

宽带数字接收机射频前端电路设计

宽带数字接收机在无线电频谱管理领域内具有重要的应用,其中射频前端电路指标对整机设备性能的影响显著。文中介绍了一种射频前端电路通用的设计方案,重点分析了各射频器件性能指标对接收机链路的影响,以及对无线电监测与测向结果的影响。最终提出了改进电路拓扑结构设计的措施与办法,并给出了基于该设计思路的具体工程应用实例,取得了良好的应用效果。     

VHF跳频电台接收机射频前端的仿真设计与研究

通过对VHF跳频电台接收机射频前端设计指标和具体结构的介绍,运用Agilent公司的射频设计仿真软件ADS,对整个接收机射频前端电路进行仿真和电路设计,构建了一个由保护电路、跳频预选滤波器、低噪声放大器和自动增益控制电路组成的射频前端电路模型,并对其进行仿真.最后的实验结果表明,所设计的射频前端的性能指标达到了系统的设计要求,并有所提高.     

接收机射频前端噪声特性分析

噪声是影响接收机灵敏度的重要因素之一。接收机引入的噪声越小,接收机灵敏度就越高。分析了接收机噪声,给出了射频前端噪声系数与接收机灵敏度的关系,论述了几种改善射频前端噪声系数的方法。     

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.     

Design and measurements of a RF front-end for Bi-band simultaneous reception

In this paper, we explore spectrum field band simultaneous receivers, with a special emphasis on only one aspect of these systems – the radio front-end. We propose, to validate in the lab, a receiver scheme for the simultaneous down-conversion of two signals in different bands. Obviously, the dedicated scheme is intended for practical use in an integrated circuit. In this work, the chosen receiver is implemented with discrete components. A test set is evaluated and compared to simulations; it contains mostly standard lab equipment, processing signals, according to the receiver scheme; this receiver presents merits and it is worth demonstrating in an integrated circuit.In order to give credit to the use of this type of receiver, the EDA model and results have to be validated by measurement. Therefore, based on the receiver architecture dedicated to an 802.11/UMTS simultaneous dual-channel processing, we design and fabricate a prototype. Firstly, we measure the intrinsic metrics of this prototype in terms of noise figure, gain, linearity, phase and gain mismatch between the two branches of the quadrature mounted mixers. In the present work, we demonstrate that, for instance, as NF and IIP3 change with the RF front-end gain with the improvement of the RF front-end performance, the linearity and the noise requirements are well handled. Afterwards, these metrics are injected in the EDA receiver model and simulations are done in order to evaluate the BER evolution.     

L波段集成自检源小型化多通道前端

L波段射频系统的前端模块,在完成放大滤波功能的基础上,还需要具有产生自检信号的功能,以及与上位机进行通信的能力。为了适应现代社会对设备功能完备、体积小、质量轻的要求,通过选用小型集成化跳频源,将数字控制、接口电路与微波控制电路相集成,将自检功分电路与微波控制电路集成,研制出一款集成自检源的多通道射频前端。在保证原有射频前端放大滤波功能、产生自检信号功能、与上位机进行通信功能的基础上,大幅度地减小了射频前端的体积与质量。通过实物制作与测试,验证了上述设计方法在保证多通道射频前端功能完整性的情况下可以大幅度减小整体模块的体积、减轻模块的质量。     

An adaptive weaver architecture radio with spectrum sensing capabilities to relax RF component requirements

This paper presents an architecture that utilizes spectrum sensing with a Weaver architecture receiver to ease the requirements on the RF front-end components. With the ability to sense the environment, large interferers that overwhelm small desired signals can be avoided. The learning and adapting capabilities are enabled by means of a flexible receiver architecture employing variable local oscillators (LOs) at RF and intermediate frequency (IF). Avoiding large interferers can reduce image rejection ratio (IRR) requirements for a given performance and results in a greater tolerance to the Q of filters and receiver mismatches. The design approach is applied to an IEEE 802.11a receiver and the results show that for a given performance level, the proposed design requires an IRR that is 40 dB less than that required for conventional Weaver receivers