采用软/硬件协同设计的RS译码器

RS码在数字通信系统中得到了广泛的应用，本文在分析RS译码过程的原理基础上，提出了采用软／硬件协同设计的方法来实现RS译码器，并与目前已有的纯硬件方案做了性能对比。     

高性能逆变器驱动芯片BCS1608及其应用

BCS1608是博立码杰通讯（深圳）有限公司推出的单片两／三相升压逆变器。该芯片采用＋2．5～＋5．5V低电压供电．可用于在便携式仪器仪表、音频、通信等系统中。文中介绍了BCS1608的基本特性、引脚功能及使用方法，给出了芯片在微型超声电机中的应用方案。     

纠错码在数据传输系统中的应用

近年来，由于采用纠错码技术能够增强数据的容错能力，提高数据传输的可靠性，使纠错码较为普遍使用．本文旨在介绍一种在数据传输系统中利用纠错码进行数字处理的技术，对组成级联码的BCH码和RS码进行了介绍，重点分析BCH码和RS码的编译码技术，而且提出了编译码的硬件实现方面的一些想法。     

无线局域网采用的补偿码键控调制方式

采用补偿码健控（CCK）可以使IEEE802．11b无线局域网系统实现多速率通信，这是补偿码第一次用于调制。介绍了无线局域网的直接序列扩频（DSSS）的各种模式，着重介绍了无线局域网所采用的CCK调制方式，并对CCK调制的性能进行了理论上的分析。     

基于级联码的差错控制系统的设计与实现

介绍了级联码编码与译码的设计和实现。该级联码由RS码、卷积码以及郑交织器构成。编码电路可用CPLD实现，译码采用AHA4210芯片完成，速度快。编译码的各种参数和过程由软件控制，非常灵活。通过加载不同的软件可以在同一硬件平台上实现多种的级联、RS码、卷积码或是卷交织器。在工程中有很高的实用价值。     

跳频通信系统中的纠错码设计与实现

跳频通信可以通过载频在宽频带风的跳变来躲避干扰,但是在实际系统中不可避免地会受到人为的干扰,从而赞成跳频通信系统性能的下降。部分频带干扰是常用的一种方式。针对这种干扰,采用RS码作为前向纠错码（FEC）的技术方案,通过理论分析和计算,说明只有合理选择RS码的参数,就能有效地改善系统的误码性能。最后给出了DSP芯片实现RS译码器的方法。     

RS码专用芯片接口的FPGA实现

现代数字通信中RS纠错编码已得到广泛应用,专门针对RS编译码的专用芯片也因此被广泛应用.文中介绍了RS码专用芯片AHA4012B的使用方法,并且给出了用FPGA(现场可编程门阵列)实现与AHA4012B接口的方法.该接口已经在实际调制解调器电路中运用,工作稳定可靠.     

RS码在无线高保真音频传输系统中的应用

在现代社会中,随着无线技术的发展,越来越多的无线设备占据着家庭中的每一个角落。然而无线传输存在着传输带宽以及误码率等因素的限制。在无线音频传输中,想要获得高保真的效果,就必须在带宽以及误码率方面加以着重考虑。讨论了在无线传输误码率问题上RS码所带来的纠错能力以及其实现方法,并且给出了一种可行的低成本的无线音频传输系统的解决方案。     

RS编解码在FPGA上的实现

RS码具有很强的纠随机错误和突发错误的能力，因而广泛应用于各种差错控制系统中。通过介绍一种用FPGA器件实现RS[204，188]编解码的简单可行的硬件实现方法，分析了其基本原理，给出了实现过程，这种编解码适用于HDTV等数字视频系统。     

高速RS编码器的设计与实现

研究高速RS码编码器的设计与实现问题。给出了最优对偶基的计算方法,研究了用对偶基下的bit-parallel乘法器构成RS系统码编码器。用P0PGA实现了高速RS编码器,仿真结果表明编码器的吞吐率可以达到125Mbytes/s。     

A novel RS BTC coding scheme for optical communications

A novel Reed Solomon(RS) block turbo code(BTC) coding scheme of RS(63,58)×RS(63,58) for optical communications is proposed.The simulation results show that the net coding gain(NCG) of this scheme at the sixth iteration is more than that of other coding schemes at the third iteration for the bit error rate(BER) of 10-12.Furthermore,the novel RS BTC has shorter component code and rapider encoding and decoding speed.Therefore,the novel RS BTC coding scheme can be better used in high-speed long-haul optical communication systems,and the novel RS BTC can be regarded as a candidate code of the super forward error correction(super-FEC) code.Moreover,the encoding/decoding design and implementation of the novel RS BTC are also presented.     

非系统RS(31,19)编译码算法研究与FPGA实现

针对战术数据链系统低时延数据传输需求,提出一种适用于数据链系统的信道编码方案—非系统缩短码RS(31,19)。本文从MS多项式的观点讨论了非系统RS码的编码和译码算法,并对缩短RS码的编译码算法进行了研究。最后在FPGAEP3SE110上采用了一种改进的BM算法,成功实现RS(31,19)编译码复杂算法,有效提高了译码速度,简化了数据链系统硬件设计。     

基于FT2232H的USB-RS232转换模块设计

鉴于大量外围设备和软件使用RS232串口标准,为了充分利用USB的传输速度快,连接简单快捷。即插即用等优势,给出一种采用第5代USB-to-UART—FIFO器件FT2232H设计USB—RS232转换器的方案。详细介绍FT2232H的主要特点、内部结构及功能原理,给出USB／UARTRS232接口电路设计和驱动软件。与其他设计方案相比,该系统设计具有数据传输速率快,可配置2个RS232接口等优点。     

Multi-symbol-sliced dynamically reconfigurable Reed-Solomon decoder design based on unified finite-field processing element

Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, most RS decoders are implemented as dedicated application-specified integrated circuits (ASICs) based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, the RS decoding operations are usually performed by using fine-grained processing elements (PE) controlled by a programmable digital signal processing (DSP) core, which provides high flexibility. In this paper, we propose a novel m-PE multi-symbol-sliced (MSS) RS datapath structure. The m-PE RS architecture is a highly scalable design and can be dynamically reconfigured at 1-PE, 2-PE,...,m/2-PE, and m-PE modes to deliver necessary data throughput rate. With the help of the gated-clock scheme to turn off the idle PEs, the proposed runtime configurable ASIC design provides good tradeoff between the data throughput rate and the power consumption. Hence, it can save energy to extend the battery life of the portable devices. We demonstrate a prototyping design using 4 PEs by using UMC 0.18-/spl mu/m CMOS technology. The design can be dynamically reconfigured to be operated at 1-PE, 2-PE, and 4-PE modes, with performance of 140 Mb/s at 18.91 mW, 280 Mb/s at 28.77 mW, and 560 Mb/s at 48.47 mW, respectively. Compared with existing RS designs, the proposed m-PE RS decoder has better normalized area/power efficiency than most DSP-type and ASIC-type RS designs. The reconfigurable feature makes our design a good candidate for the error control coding (ECC) unit of the storage system in power-aware portable devices.     

RS级联编码在超短波通信与卫星通信信道的仿真分析

超短波波段数据通信与卫星通信已被广泛应用。在这些信道中都存在较强的多径衰落,并且为克服两个波段中的多种干扰,纠正随机错误和突发错误,RS编码被普遍选为信道编码方案。RS码是线性分组码中纠突发错误能力最强,效率最高的编码,Turbo码是可以接近香农限的编码方案。文章提出RS编码与Turbo码的级联码编码方案和解码算法,适当选择参数,并通过仿真验证了方案的正确性与可行性。     

无线ATM系统的混合纠错方案及其在突发信道上的性能分析

本文提出了一种适用于无线ATM系统的混合纠错方案:用RS码保护话音信号,用截短RS/混合Ⅱ型ARQ保护图像和数据。文中分析和仿真了这一混合纠错方案在突发信道上的性能。结果表明,利用RS码强的纠错能力,通过有限次的重传就可获得低的信元丢失率和传输时延。     

Forced sequence sequential decoding: a concatenated coding systemwith iterated sequential inner decoding

We describe a new concatenated decoding scheme based on iterations between an inner sequentially decoded convolutional code of rate R=1/4 and memory M=23, and block interleaved outer Reed-Solomon (RS) codes with nonuniform profile. With this scheme decoding with good performance is possible as low as E_b/N₀=0.6 dB, which is about 1.25 dB below the signal-to-noise ratio (SNR) that marks the cutoff rate for the full system. Accounting for about 0.45 dB due to the outer codes, sequential decoding takes place at about 1.7 dB below the SNR cutoff rate for the convolutional code. This is possible since the iteration process provides the sequential decoders with side information that allows a smaller average load and minimizes the probability of computational overflow. Analytical results for the probability that the first RS word is decoded after C computations are presented. These results are supported by simulation results that are also extended to other parameters     

An erasure-based scheme for reduction of PAPR in spatial multiplexing MIMO-OFDM using Reed-Solomon codes over GF(216 + 1)

In this paper, a novel erasure-based scheme which uses long Reed-Solomon (RS) codes over GF(65537) is proposed for the reduction of the peak-to-average power ratio (PAPR) in coded orthogonal frequency division multiplexing (OFDM). The motivation for using the field GF(65537) is to generate long code words (up to 65536 symbols in just one code word). Using long codes results in greater flexibility to search for low PAPR OFDM frames within the subsets of symbols of a code word because RS codes are maximum distance separable and any subset of a high enough number of symbols is sufficient for the recovery of data. Over this field, the lengths of code words are exponents of 2. Hence, low-complexity radix-2 fast Fourier transform can be exploited. RS codes are deployed for both PAPR reduction and error correction. Simulation results show that in similar PAPR reduction performances, the proposed scheme outperforms the previously reported work with RS codes in both error correction and computation complexity. The proposed scheme can be applied to both single-input single-output and multi-input multi-output systems.     

10- and 40-Gb/s forward error correction devices for optical communications

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.     

Outage Probability Analysis of Three-User Reed–Solomon Coded Cooperation Scheme for Wireless Slow Fading Channel

In a coded cooperation scheme, the relay must decode and re-encode data. This process needs to be completed rapidly. Therefore, a simple channel coding/decoding scheme that requires low computational loads is needed. Reed–Solomon (RS) codes are simple, forward error-correction codes with low decoding computational loads. This paper introduces a three-user RS coded cooperation scheme that aims to have simple encoding/decoding complexity as well as to increase diversity order. It also presents the mathematical derivations of outage probability and investigates the outage performance of the three-user RS coded cooperation scheme. The derived outage probability expressions prove that the three-user RS coded cooperation scheme can achieve full diversity. Numerical bit error rate comparisons show that the three-user RS coded cooperation scheme performs better than a two-user scheme under various inter-user and uplink channel conditions. Outage probability performance improves at approximately 5 dB for regions with low signal-to-noise ratio (SNR) and 10 dB for regions with high SNR under a slow-fading channel. The paper also presents the complete calculated numerical tables for outage probability terms (integral terms) that do not have closed-form solutions.