A fully digital noncoherent and coherent GMSK receiver architecturewith joint symbol timing error and frequency offset estimation

We propose a fully digital noncoherent and coherent Gaussian minimum shift keying (GMSK) receiver architecture with joint frequency offset compensation and symbol timing recovery. Carrier phase offset can be estimated if the coherent demodulation mode is adopted. The converted base-band complex signal is first frequency discriminated and then passed through a digital filter which performs a fast Fourier transform (FFT). The frequency offset can be estimated from the DC component of the FFT, and the symbol timing error can be estimated from the phase angle of the FFT at a specified frequency which is equal to an integral multiple of half the bit rate. These two estimated parameters are then used for frequency offset compensation and symbol timing recovery during a preamble period. Coarse carrier phase can be estimated by averaging sampled in-phase and quadrature-phase signals and finding its phase angle within the preamble period after carrier frequency offset is estimated and compensated. The bit error rate (BER) performance of this GMSK receiver architecture is assessed for an additive white Gaussian noise (AWGN) channel by computer simulation     

Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/s

This letter presents a coherent digital polarization diversity receiver for real-time polarization-multiplexed synchronous quadrature phase-shift keying transmission with distributed feedback lasers at a data rate of 2.8 Gb/s. The tolerance against fast polarization changes and polarization-dependent loss is evaluated for different filter widths in the carrier recovery circuit. The minimum achieved bit-error rate is 3.4 times 10^-7.     

A digital coherent receiver suitable for land-mobile satellitecommunications

Describes an advanced coherent demodulation technique suitable for land-mobile satellite communications. The proposed technique features a combined narrow/wide band dual open loop (DOL) carrier phase estimator, which effectively enables the coherent receiver to track fast phase fluctuations caused by fading, without degradation in phase slip characteristics. Additionally, an open loop phase estimator has inherent quick recovery performance. Its bit error rate (BER) performance is shown to be superior to that for existing detection schemes, achieving a 10^-2 BER at 6.3 dB E_b/N₀ (0.9 dB greater than the theoretical E_b/N₀ condition for perfect carrier phase tracking) for QPSK over a Rician fading channel with the 10 dB Rician factor and the 1/16 baud rate fading pitch. The paper also describes a quick bit timing recovery scheme, with interpolation, featuring an open loop structure. Further, it presents an experimental digital modem developed through the use of digital signal processors     

High-performance coherent demodulator LSIC for wireless personalcommunications

This paper presents a high-performance coherent π/4-shift differential quaternary phase shift keying (DQPSK) demodulator (large scale integrated circuit) LSIC for the personal communication system in Japan, which is implemented on a 2-V operation 0.8-μm CMOS standard cell. The developed LSIC achieves a better bit error rate (BER) and frame error rate (FER) performance and a lower power consumption than conventional demodulators by employing new schemes: (1) a reverse-modulation carrier recovery circuit with a -π/4 phase rotator and a bandwidth-changeable carrier filter; (2) a bit timing recovery circuit using an initial bit timing estimation scheme; and (3) a fully digital orthogonal detector suitable for low power consumption. Performance evaluation confirms that the developed demodulator LSIC reduces the irreducible frame error rate by 40% and achieves an Eb/No improvement of 3 dB at an FER of 10^-1 compared with differential detection in the Rayleigh fading typical of personal communication channels     

Noncoherent Detection of Tamed Frequency Modulation

Continuous-phase, constant-envelope digital modulation schemes are useful in various applications where a high spectrum utilization as well as immunity to nonlinear distortion is required. From this point of view, typical efficient schemes are digital partialresponse frequency modulation methods. The aim of this work is to investigate noncoherent detection in order to avoid the RF carrier recovery problem. In this paper we select for analysis tamed frequency modulation (TFM) as a particularly representative member of this class, but a similar analysis could be carried out for other partialresponse digital FM systems. After an evaluation of the optimal noncoherent detection and of differential phase detection of TFM, we propose a demodulation method based on a simple and efficient baseband processing of the output of a frequency demodulator. It turns out that the power loss with respect to coherent or optimal demodulation of TFM is on the order of 2 dB. The baseband processing here proposed is in some way equivalent to a partial recovery of the carrier phase and could be improved by using a more complex baseband processing such as a decoding scheme based on the Viterbi algorithm.     

A single-chip MSK coherent demodulator for mobile radio transmission

Design and performance of a single-chip minimum shift keying (MSK) coherent demodulator fabricated by complementary metal oxide semiconductor-integrated circuit (CMOS-IC) technology is described. The demodulator consists of a phase detection circuit, carrier recovery circuit, data recovery circuit, and timing-clock recovery circuit. For the carrier recovery circuit, three types of Costas-loop are reviewed from the viewpoint that MSK modulation format has a close relationship to binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK). Among these loops, a loop of center-frequency locking scheme modified from a BPSK Costas-loop, termed MSK Costas-loop in this paper, is adopted for IC implementation. Digital IC design techniques are next described. Utilizing the sample-and-hold operation of the digital devices, a divided-frequency locking scheme of the quadrature coherent demodulation is proposed. Finally, IC demodulator performance is experimentally shown in the static and Rayleigh fading environments. The bit error rate performance and error-burst characteristic are measured. It is concluded that the single-chip coherent demodulator is suitable for digital mobile radio application.     

All-digital reverse modulation architecture based carrier recoveryimplementation for GMSK and compatible FQPSK

A carrier recovery circuit implementation with an all-digital reverse modulation approach for coherent detection in the GSM/GMSK system as well as the GMSK compatible improved efficiency cross-correlated FQPSK system is presented. The proposed carrier recovery implementation utilizes all-digital reverse modulation circuit in a feedback loop to remove the modulated signal from the received intermediate frequency (IF) signal and to estimate the phase error of this carrier signal using a phase-locked loop (PLL). The digital reverse modulation approach avoids the multipliers required in an analog reverse modulation design, so that it can be implemented in a single chip FPGA. Hardware implementation of the coherent detection demonstrates that cross-correlated FQPSK is completely compatible with GMSK in the system performance and the receiver structure for GSM. Experimental performance evaluations show that the proposed carrier recovery circuit provides a Bit Error Rate (BER) performance within 0.3 dB in a non-linearly amplified channel corrupted by additive white Gaussian noise (AWCN) as compared with the simulated performance of the GSM/GMSK system     

Fast carrier-tracking coherent detection with dual-mode carrierrecovery circuit for digital land mobile radio transmission

A new type of carrier recovery circuit suitable for coherent detection in digital land-mobile radio transmission is studied experimentally. A dual-mode carrier recovery (DCR) circuit is proposed that adaptively selects one of two phase locked-loop operation modes: the conventional mode or the adaptive carrier-tracking (ACT) mode. The ACT mode digitally controls the reference phase, and enables instantaneous phase tracking in burst signal operation and/or in a fast fading environment. The DCR coherent demodulator performance is identical to that of conventional coherent detection in the low-CNR region, and to that of differential detection in the high CNR region where the ACT mode is selected     

基于多相滤波的PCM/FM正交解调

传统的相干正交解调方法,需要提取同频同相的载波,从而增加了解调的难度。根据遥测系统脉冲编码调制/调频（PCM/FM,Pulse Code Modulation-Frequency Modulation）信号的特点,采用基于多相滤波的解调方法。该方法通过多相滤波的方式来实现正交变换,不需要在接收端恢复同频同相的载波,从而降低了传统解调方法中电路实现的难度。通过MATLAB对信号进行调制解调的仿真,比较了不同解调方法对信号的解调效果,并在表格中显示了解调的误码率数据,从而验证了该方法的可行性和优越性。     

音频MFSK数字解调算法设计及DSP实现

针对音频多进制数字频率调制MFSK信号的特点,设计了一种适用于全数字接收机的非相干数字解调算法。算法主要包括数字滤波、数字变频、求瞬时相位、求瞬时频率、中值滤波、抽取和定时恢复环路几部分。重点介绍MFSK多电平基带的码元定时恢复环路的设计方法,对解调中要注意的几个问题进行了强调说明。在对解调性能进行仿真的基础上,在DSP硬件平台上进行了物理实现验证。     

Hypercube-based architecture for high speed communication systems

An implementation is presented of digital demultiplexing and demodulation algorithms for an advanced satellite communication system on a hypercube. The mapping on a hypercube provides the high speed necessary for processing hundreds of single channel per carrier/frequency division multiple access (SCPC/FDMA) voice/data channels. Data demultiplexing and demodulation are parts of the recovery of the transmitted digital data in a MODEM. A demultiplexer comprises a filter bank followed by the computation of FFT. A demodulator primarily consists of circuits to recovery carrier signal, clock frequency and data. The computation of FFT on a hypercube is well established (Hwang and Briggs 1984). Therefore, this paper analyses the filter bank and carrier and data recovery algorithms to find an efficient mapping in a multiprocessor environment connected in a hypercubic configuration. A few models to implement these algorithms on a hypercube are provided. Comparison of the speed-up achieved on a hypercube vrsus that on a sequential computer is provided for the three models.     

Performance Optimization of High Order QAM in Presence of Phase Noise and AWGN: Application to a Decision Directed Frequency Synchronization System

The paper presents an analysis of the impact of Local Oscillators (LO) phase noise on the performance of digital transmission systems. Using an efficient phase noise model, we study degradations induced by phase noise and Additive White Gaussian Noise (AWGN) on a carrier recovery system combined to high order Quadrature Amplitude Modulations (QAM). Simulation results show that an optimum trade-off between AWGN and phase noise robustness for the loop bandwidth can be determined. In order to compare simulated and analytical performance, a new general expression of the bit error probability is developped for square QAM in the presence of phase noise over Gaussian channel. Furthermore, novel decision areas related to Quadrature Amplitude Modulations are determined in order to improve the performance of the carrier recovery algorithm in the presence of phase noise and frequency offset.     

Digital frequency estimation in burst mode QPSK transmission

In burst digital transmission using PSK (phase shift keying) modulation with coherent detection, the recovery of the carrier reference phase and the symbol clock is a key aspect. If all users have a common clock synchronization, symbol timing needs not to be recovered in each burst. A digital processor for carrier recovery without preambles, in the presence of frequency offset, is considered. As an example, a 2 Mb/s QPSK transmission system is considered in which E _b/N_o=10 dB, and the burst and estimation interval length L=15. Using the algorithm described and averaging eight successive estimated frequency offsets, in order to eliminate anomalous errors, the BER (bit error rate) degradation is equal to 0.14 dB when Δf=20 kHz     

高速8-PSK的PFD载波恢复设计

设计一种基于8PSK调制方案的锁频锁相器载波恢复环路,该环路由通用载波同步鉴相算法结合PFD算法,实现了大频偏的捕获和获得较小的稳态相位抖动。提出针对MPSK调制方案的PFD的两种加窗方法,选择较优的方案进行了性能仿真。结果表明,该载波恢复方案具有捕获频偏大、稳态相差小、稳定性高的特点,是一种非常适合于卫星通信的高速8PSK调制的载波恢复方案。     

QAM全数字接收机载波相位恢复环路

本文着重研究全数字QAM接收机中载波恢复环路的设计，采用快慢两个数字环路来进行载波恢复，慢环路由锁频器（Frequency Detector)，锁频锁相器（Phase and Frequency Detector)等组成，快环路由相痊解旋器和锁相器（Phase Detector)组成，仿真结果表明，在AWGN条件下，两个环路的环路参数设置存在一个最佳点，当两个环路工作在这个最佳点附近时接收机能够很好的进行载波频率，相位的恢复，相位噪声对接收机性能的影响最小，最后，给出了在不同信噪比下的最佳环路参数表。     

软件接收机中DSB-SC信号载波同步的一种算法

本文提出了软件妆收机中抑制载波双边带调幅（DSB-SC）信号载波同步的一种算法，根据下变频后的基带信号估计出收发载波的频差，并经卡尔曼滤波后结合数字锁相环以达到载波捕获范围宽、跟踪速度快、环路噪声小的特点。文章最后给出了一个具体实例的仿真结果。     

A Carrier Recovery Approach for ATSC Receivers

This paper presents a method of using the field sync signal to perform carrier recovery for ATSC receivers. This approach ensures a fast, reliable, and accurate receiver carrier frequency and phase recovery even under severely distorted channel conditions.     

一种WCDMA MT的数字载波跟踪环路设计

本文讨论了一种用于W CDMA MT的数字载波跟踪环路。它利用W CDMA系统的导频信号,实现了一种鉴频鉴相环路。计算机仿真结果显示该环路可以保证可靠的载波恢复。     

无线电台中DS/D-MPSK调制解调器的FPGA实现

提出了一种通用数字DS/D-MPSK调制和解扩解调器的实现方案。该方案采用了成型滤波、直接数字合成(DDS)、正交调制、数字匹配滤波和延时差分解调等技术,直接在中频上进行数字信号处理,不需要进行数字下变频,也不需要进行伪随机码同步捕获和载波提取,简单易行,具有一定的新意和较高的实用价值。本方案已经应用于某军用超短波电台中,验证了方案的正确性和可行性。     

Mixed-signal quadrature demodulator with a multicarrierregeneration system

This paper presents a combined analog/digital demodulation system built around a (PLL) with digital carrier regeneration. The input signal itself is not digitized, but the PLL is digital wherever it is possible. The link between the analog and the digital domain is a 1-bit sigma-delta converter that converts the (quasi-dc) output signal of the PLL's phase detector into a bitstream. The PLL's loop filter doubles as a decimation filter for the bitstream. The analog I and Q output signals are obtained by multiplying the analog input signal with the digital output signal of the PLL in two four-quadrant multiplying digital-to-analog converters